Michael J. Collins

Person

Tomball, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Computer system with adaptive memory arbitration scheme
- Patent number 6,505,260
- Issue date Jan 7, 2003
- Compaq Information Technologies Group, L.P.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrently requesting input/output and memo...
- Patent number 6,356,972
- Issue date Mar 12, 2002
- Compaq Information Technologies Group, L.P.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with adaptive memory arbitration scheme
- Patent number 6,286,083
- Issue date Sep 4, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with improved memory access
- Patent number 6,279,065
- Issue date Aug 21, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for maintaining ownership of a processor bus whil...
- Patent number 6,275,885
- Issue date Aug 14, 2001
- Compaq Computer Corp.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improving processor read latency in a system...
- Patent number 6,272,651
- Issue date Aug 7, 2001
- Compaq Computer Corp.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with synchronous memory arbiter that permits asynch...
- Patent number 6,249,847
- Issue date Jun 19, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system employing memory controller and bridge interface pe...
- Patent number 6,247,102
- Issue date Jun 12, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for optimally deferring or retrying a cycle upon...
- Patent number 6,216,190
- Issue date Apr 10, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system controller and method with processor write posting...
- Patent number 6,209,067
- Issue date Mar 27, 2001
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for suppressing processor cycles to memory until...
- Patent number 6,209,052
- Issue date Mar 27, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrently requesting input/output and memo...
- Patent number 6,202,101
- Issue date Mar 13, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for aligning an initial cache line of data read f...
- Patent number 6,199,118
- Issue date Mar 6, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for aligning an initial cache line of data read f...
- Patent number 6,160,562
- Issue date Dec 12, 2000
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical cache system flushing scheme based on monitoring and d...
- Patent number 6,115,791
- Issue date Sep 5, 2000
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated graphics port multiple entry gart cache allocation syst...
- Patent number 5,949,436
- Issue date Sep 7, 1999
- Compaq Computer Corporation
- Ronald T. Horan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller including write posting queues, bus read control...
- Patent number 5,938,739
- Issue date Aug 17, 1999
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sense amplifier decoding in a memory device to reduce power consump...
- Patent number 5,848,428
- Issue date Dec 8, 1998
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single bank, multiple way cache memory
- Patent number 5,835,948
- Issue date Nov 10, 1998
- Compaq Computer Corporation
- Sompong P. Olarig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System in which processor interface snoops first and second level c...
- Patent number 5,819,105
- Issue date Oct 6, 1998
- Compaq Computer Corporation
- Michael P. Moriarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Burst SRAMs for use with a high speed clock
- Patent number 5,809,549
- Issue date Sep 15, 1998
- Compaq Computer Corp.
- Gary W. Thome
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for switching between synchronous and asynchronous memory r...
- Patent number 5,796,992
- Issue date Aug 18, 1998
- Compaq Computer Corporation
- James R. Reif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory using unique burst counter circuitry and asynchronous...
- Patent number 5,793,693
- Issue date Aug 11, 1998
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of preventing cache corruption during microprocessor pipelin...
- Patent number 5,781,925
- Issue date Jul 14, 1998
- Compaq Computer Corporation
- John E. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable memory controller having two level look-up for memory...
- Patent number 5,778,413
- Issue date Jul 7, 1998
- Compaq Computer Corporation
- Jeffrey C. Stevens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system including a first level write-back cache and a seco...
- Patent number 5,778,433
- Issue date Jul 7, 1998
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for entering low power mode in a computer system
- Patent number 5,721,935
- Issue date Feb 24, 1998
- Compaq Computer Corporation
- Todd J. DeSchepper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a plurality of posting queues associated with differe...
- Patent number 5,634,073
- Issue date May 27, 1997
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Burst SRAMS for use with a high speed clock
- Patent number 5,604,884
- Issue date Feb 18, 1997
- Compaq Computer Corporation
- Gary W. Thome
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical cache system flushing scheme based on monitoring and d...
- Patent number 5,581,727
- Issue date Dec 3, 1996
- Compaq Computer Corporation
- Michael J. Collins
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Computer system with adaptive memory arbitration scheme
- Publication number 20010010066
- Publication date Jul 26, 2001
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING

Michael J. Collins

Person

Patents Grantslast 30 patents

Computer system with adaptive memory arbitration scheme

System and method for concurrently requesting input/output and memo...

Computer system with adaptive memory arbitration scheme

Computer system with improved memory access

System and method for maintaining ownership of a processor bus whil...

System and method for improving processor read latency in a system...

Computer system with synchronous memory arbiter that permits asynch...

Computer system employing memory controller and bridge interface pe...

System and method for optimally deferring or retrying a cycle upon...

Computer system controller and method with processor write posting...

System and method for suppressing processor cycles to memory until...

System and method for concurrently requesting input/output and memo...

System and method for aligning an initial cache line of data read f...

System and method for aligning an initial cache line of data read f...

Hierarchical cache system flushing scheme based on monitoring and d...

Accelerated graphics port multiple entry gart cache allocation syst...

Memory controller including write posting queues, bus read control...

Sense amplifier decoding in a memory device to reduce power consump...

Single bank, multiple way cache memory

System in which processor interface snoops first and second level c...

Burst SRAMs for use with a high speed clock

Circuit for switching between synchronous and asynchronous memory r...

Cache memory using unique burst counter circuitry and asynchronous...

Method of preventing cache corruption during microprocessor pipelin...

Programmable memory controller having two level look-up for memory...

Computer system including a first level write-back cache and a seco...

Apparatus and method for entering low power mode in a computer system

System having a plurality of posting queues associated with differe...

Burst SRAMS for use with a high speed clock

Hierarchical cache system flushing scheme based on monitoring and d...

Patents Applicationslast 30 patents

Computer system with adaptive memory arbitration scheme