Michael J. Jackson

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,610,995
- Issue date Mar 21, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,482,618
- Issue date Oct 25, 2022
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial source or drain structures for advanced integrated circui...
- Patent number 11,411,095
- Issue date Aug 9, 2022
- Intel Corporation
- Subhash Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS and PMOS str...
- Patent number 11,411,110
- Issue date Aug 9, 2022
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS structures
- Patent number 11,107,920
- Issue date Aug 31, 2021
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dislocation enhanced strain in NMOS structures
- Patent number 10,396,201
- Issue date Aug 27, 2019
- Intel Corporation
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tin doped III-V material contacts
- Patent number 9,966,440
- Issue date May 8, 2018
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor fabrication technique including sacrificial protective l...
- Patent number 9,633,835
- Issue date Apr 25, 2017
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tin doped III-V material contacts
- Patent number 8,896,066
- Issue date Nov 25, 2014
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...
- Publication number 20250126869
- Publication date Apr 17, 2025
- Intel Corporation
- Subhash JOSHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20230197848
- Publication date Jun 22, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20230006063
- Publication date Jan 5, 2023
- Daedalus Prime LLC
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...
- Publication number 20220344494
- Publication date Oct 27, 2022
- Intel Corporation
- Subhash JOSHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20220238714
- Publication date Jul 28, 2022
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...
- Publication number 20220059699
- Publication date Feb 24, 2022
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
- Publication number 20190334034
- Publication date Oct 31, 2019
- Intel Corporation
- Michael JACKSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...
- Publication number 20190165172
- Publication date May 30, 2019
- Intel Corporation
- Subhash JOSHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE L...
- Publication number 20170229342
- Publication date Aug 10, 2017
- Intel Corporation
- GLENN A. GLASS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
- Publication number 20160204256
- Publication date Jul 14, 2016
- Michael Jackson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE L...
- Publication number 20150069473
- Publication date Mar 12, 2015
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TIN DOPED III-V MATERIAL CONTACTS
- Publication number 20150054031
- Publication date Feb 26, 2015
- Intel Corporation
- GLENN A. GLASS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TIN DOPED III-V MATERIAL CONTACTS
- Publication number 20130154016
- Publication date Jun 20, 2013
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS

Michael J. Jackson

Person

Patents Grantslast 30 patents

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Epitaxial source or drain structures for advanced integrated circui...

Methods of forming dislocation enhanced strain in NMOS and PMOS str...

Methods of forming dislocation enhanced strain in NMOS structures

Methods of forming dislocation enhanced strain in NMOS structures

Tin doped III-V material contacts

Transistor fabrication technique including sacrificial protective l...

Tin doped III-V material contacts

Patents Applicationslast 30 patents

EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STR...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES

EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUI...

TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE L...

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES

TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE L...

TIN DOPED III-V MATERIAL CONTACTS

TIN DOPED III-V MATERIAL CONTACTS