Michael J. Tresidder

Person

Spicewood, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses, systems, and methods for multi-lane data bus inversion
- Patent number 12,174,775
- Issue date Dec 24, 2024
- Advanced Micro Devices, Inc.
- Padmini Nujetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Droop mitigation for an inter-chiplet interface
- Patent number 12,147,366
- Issue date Nov 19, 2024
- Advanced Micro Devices, Inc.
- Michael J. Tresidder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skew matching in a die-to-die interface
- Patent number 11,960,435
- Issue date Apr 16, 2024
- Advanced Micro Devices, Inc.
- Pradeep Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for data scrambling
- Patent number 11,693,465
- Issue date Jul 4, 2023
- Advanced Micro Devices, Inc.
- Yanfeng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing chiplet wakeup latency
- Patent number 11,281,280
- Issue date Mar 22, 2022
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskewing method for a physical layer interface on a multi-chip module
- Patent number 11,283,589
- Issue date Mar 22, 2022
- Advanced Micro Devices, Inc.
- Varun Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for physical layer bypass
- Patent number 11,132,327
- Issue date Sep 28, 2021
- ATI Technologies ULC
- Michael J. Tresidder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for data scrambling
- Patent number 10,895,901
- Issue date Jan 19, 2021
- ADVANCED MICRO DEVICES INC.
- Yanfeng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskewing method for a physical layer interface on a multi-chip module
- Patent number 10,873,445
- Issue date Dec 22, 2020
- Advanced Micro Devices, Inc.
- Varun Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing chiplet wakeup latency
- Patent number 10,656,696
- Issue date May 19, 2020
- Advanced Micro Devices, Inc.
- Benjamin Tsien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskewing method for a physical layer interface on a multi-chip module
- Patent number 10,581,587
- Issue date Mar 3, 2020
- Advanced Micro Devices, Inc.
- Varun Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hardware transmit equalization for high speed
- Patent number 10,541,841
- Issue date Jan 21, 2020
- Advanced Micro Devices, Inc.
- Shiqi Sun
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Offset Data Integrity Checks for Latency Reduction
- Publication number 20240095404
- Publication date Mar 21, 2024
- ADVANCED MICRO DEVICES, INC.
- Shaofeng An
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DROOP MITIGATION FOR AN INTER-CHIPLET INTERFACE
- Publication number 20240004821
- Publication date Jan 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Michael J. Tresidder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING TRAINING OF AN INTER-CHIPLET INTERFACE
- Publication number 20240004815
- Publication date Jan 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Michael J. Tresidder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC PROVISION OF HIGH SPEED SERIALIZER/DESERIALIZER LANES BY...
- Publication number 20240004822
- Publication date Jan 4, 2024
- ADVANCED MICRO DEVICES, INC.
- George D. Azevedo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SKEW MATCHING IN A DIE-TO-DIE INTERFACE
- Publication number 20230195678
- Publication date Jun 22, 2023
- ADVANCED MICRO DEVICES, INC.
- PRADEEP JAYARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DATA SCRAMBLING
- Publication number 20210132675
- Publication date May 6, 2021
- ADVANCED MICRO DEVICES, INC.
- Yanfeng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESKEWING METHOD FOR A PHYSICAL LAYER INTERFACE ON A MULTI-CHIP MODULE
- Publication number 20210111861
- Publication date Apr 15, 2021
- ADVANCED MICRO DEVICES, INC.
- Varun Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
REDUCING CHIPLET WAKEUP LATENCY
- Publication number 20200387208
- Publication date Dec 10, 2020
- ADVANCED MICRO DEVICES, INC.
- Benjamin Tsien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESKEWING METHOD FOR A PHYSICAL LAYER INTERFACE ON A MULTI-CHIP MODULE
- Publication number 20200344039
- Publication date Oct 29, 2020
- ADVANCED MICRO DEVICES, INC.
- Varun Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR PHYSICAL LAYER BYPASS
- Publication number 20200174962
- Publication date Jun 4, 2020
- ADVANCED MICRO DEVICES, INC.
- Michael J. Tresidder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC FINE GRAIN LINK CONTROL
- Publication number 20190158374
- Publication date May 23, 2019
- ADVANCED MICRO DEVICES, INC.
- Alexander J. Branover
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Michael J. Tresidder

Person

Patents Grantslast 30 patents

Apparatuses, systems, and methods for multi-lane data bus inversion

Droop mitigation for an inter-chiplet interface

Skew matching in a die-to-die interface

Method and apparatus for data scrambling

Reducing chiplet wakeup latency

Deskewing method for a physical layer interface on a multi-chip module

Method and apparatus for physical layer bypass

Method and apparatus for data scrambling

Deskewing method for a physical layer interface on a multi-chip module

Reducing chiplet wakeup latency

Deskewing method for a physical layer interface on a multi-chip module

Hardware transmit equalization for high speed

Patents Applicationslast 30 patents

Offset Data Integrity Checks for Latency Reduction

DROOP MITIGATION FOR AN INTER-CHIPLET INTERFACE

SCHEDULING TRAINING OF AN INTER-CHIPLET INTERFACE

AUTOMATIC PROVISION OF HIGH SPEED SERIALIZER/DESERIALIZER LANES BY...

SKEW MATCHING IN A DIE-TO-DIE INTERFACE

METHOD AND APPARATUS FOR DATA SCRAMBLING

DESKEWING METHOD FOR A PHYSICAL LAYER INTERFACE ON A MULTI-CHIP MODULE

REDUCING CHIPLET WAKEUP LATENCY

DESKEWING METHOD FOR A PHYSICAL LAYER INTERFACE ON A MULTI-CHIP MODULE

METHOD AND APPARATUS FOR PHYSICAL LAYER BYPASS

DYNAMIC FINE GRAIN LINK CONTROL