Michael J. Tripp

Person

Forest Grove, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Technique to create link determinism
- Patent number 7,747,888
- Issue date Jun 29, 2010
- Intel Corporation
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to self-test single and multi-core CPU systems
- Patent number 7,463,992
- Issue date Dec 9, 2008
- Intel Corporation
- Samie B. Samaan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to create link determinism
- Patent number 7,328,359
- Issue date Feb 5, 2008
- Intel Corporation
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for validating AC I/O loopback tests using...
- Patent number 7,228,515
- Issue date Jun 5, 2007
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic self test of an integrated circuit component via AC I/O l...
- Patent number 7,139,957
- Issue date Nov 21, 2006
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device testing
- Patent number 6,885,209
- Issue date Apr 26, 2005
- Intel Corporation
- Tak M. Mak
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory cell structural test
- Patent number 6,757,209
- Issue date Jun 29, 2004
- Intel Corporation
- Tak M. Mak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory addressing structural test
- Patent number 6,721,216
- Issue date Apr 13, 2004
- Intel Corporation
- Tak M. Mak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to structurally detect random defects that imp...
- Patent number 6,629,274
- Issue date Sep 30, 2003
- Intel Corporation
- Mike Tripp
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a logic device
- Patent number 6,615,379
- Issue date Sep 2, 2003
- Intel Corporation
- Michael J. Tripp
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for conducting input/output loop back tests us...
- Patent number 6,477,674
- Issue date Nov 5, 2002
- Intel Corporation
- Sarah E. Bates
- G01 - MEASURING TESTING
Information Patent Grant
Microprocessor with an external command mode for diagnosis and debu...
- Patent number 5,479,652
- Issue date Dec 26, 1995
- Intel Corporation
- Robert S. Dreyer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT
- Publication number 20140156892
- Publication date Jun 5, 2014
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to self-test single and multi-core CPU systems
- Publication number 20080082285
- Publication date Apr 3, 2008
- Samie B. Samaan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to create link determinism
- Publication number 20080065924
- Publication date Mar 13, 2008
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system, and apparatus for link latency management
- Publication number 20060168379
- Publication date Jul 27, 2006
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to create link determinism
- Publication number 20060020843
- Publication date Jan 26, 2006
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for validating AC I/O loopback tests using...
- Publication number 20050257185
- Publication date Nov 17, 2005
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic self test of an integrated circuit component via AC I/O l...
- Publication number 20040267479
- Publication date Dec 30, 2004
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device testing
- Publication number 20040036494
- Publication date Feb 26, 2004
- Tak M. Mak
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory addressing structural test
- Publication number 20020141276
- Publication date Oct 3, 2002
- Tak M. Mak
- G11 - INFORMATION STORAGE
Information Patent Application
Memory cell structural test
- Publication number 20020141259
- Publication date Oct 3, 2002
- Tak M. Mak
- G11 - INFORMATION STORAGE

Michael J. Tripp

Person

Patents Grantslast 30 patents

Technique to create link determinism

Method and system to self-test single and multi-core CPU systems

Technique to create link determinism

Methods and apparatuses for validating AC I/O loopback tests using...

Automatic self test of an integrated circuit component via AC I/O l...

Device testing

Memory cell structural test

Memory addressing structural test

Method and apparatus to structurally detect random defects that imp...

Method and apparatus for testing a logic device

Method and apparatus for conducting input/output loop back tests us...

Microprocessor with an external command mode for diagnosis and debu...

Patents Applicationslast 30 patents

METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT

Method and system to self-test single and multi-core CPU systems

Technique to create link determinism

Method, system, and apparatus for link latency management

Technique to create link determinism

Methods and apparatuses for validating AC I/O loopback tests using...

Automatic self test of an integrated circuit component via AC I/O l...

Device testing

Memory addressing structural test

Memory cell structural test