Michael Jacob

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing memory failures in integrated circuits
- Patent number 7,187,602
- Issue date Mar 6, 2007
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device having semiconductor memory with sense amplifier
- Patent number 7,142,473
- Issue date Nov 28, 2006
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell signal window testing apparatus
- Patent number 6,999,887
- Issue date Feb 14, 2006
- Infineon Technologies AG
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing effects of noise coupling in integrated circuits with memo...
- Patent number 6,920,059
- Issue date Jul 19, 2005
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having semiconductor memory with sense amplifier
- Patent number 6,898,104
- Issue date May 24, 2005
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing test circuit
- Patent number 6,885,597
- Issue date Apr 26, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
2T2C signal margin test mode using a defined charge exchange betwee...
- Patent number 6,876,590
- Issue date Apr 5, 2005
- Infineon Technologies, AG
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory integrated circuit with improved reliability
- Patent number 6,858,890
- Issue date Feb 22, 2005
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory integrated circuit
- Patent number 6,795,329
- Issue date Sep 21, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable capacitances for memory cells within a cell group
- Patent number 6,731,529
- Issue date May 4, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
2T2C signal margin test mode using resistive element
- Patent number 6,731,554
- Issue date May 4, 2004
- Infineon Technologies AG
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with memory cell groups
- Patent number 6,724,026
- Issue date Apr 20, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Historical information storage for integrated circuits
- Patent number 6,707,699
- Issue date Mar 16, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Klaus Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture
- Patent number 6,639,824
- Issue date Oct 28, 2003
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor device having semiconductor memory with sense amplifier
- Publication number 20050146918
- Publication date Jul 7, 2005
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Signal margin test mode for FeRAM with ferroelectric reference capa...
- Publication number 20050063213
- Publication date Mar 24, 2005
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Reference circuit implemented to reduce the degradation of referenc...
- Publication number 20050063212
- Publication date Mar 24, 2005
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
High density flash memory with high speed cache data interface
- Publication number 20050050261
- Publication date Mar 3, 2005
- Thomas Roehr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory cell signal window testing apparatus
- Publication number 20050033541
- Publication date Feb 10, 2005
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing effects of noise coupling in integrated circuits with memo...
- Publication number 20040105293
- Publication date Jun 3, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C signal margin test mode using a defined charge exchange betwee...
- Publication number 20040095821
- Publication date May 20, 2004
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT
- Publication number 20040095820
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C signal margin test mode using different pre-charge levels for...
- Publication number 20040095799
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory architecture
- Publication number 20040095798
- Publication date May 20, 2004
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device having semiconductor memory with sense amplifier
- Publication number 20040090826
- Publication date May 13, 2004
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS
- Publication number 20040057273
- Publication date Mar 25, 2004
- Michael Klaus Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS
- Publication number 20040056286
- Publication date Mar 25, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Sensing test circuit
- Publication number 20040047171
- Publication date Mar 11, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Memory integrated circuit
- Publication number 20030237011
- Publication date Dec 25, 2003
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Variable capacitances for memory cells within a cell group
- Publication number 20030223263
- Publication date Dec 4, 2003
- Michael Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ferroelectric memory integrated circuit with improved reliability
- Publication number 20030222279
- Publication date Dec 4, 2003
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing Memory Failures in Integrated Circuits
- Publication number 20030179616
- Publication date Sep 25, 2003
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING

Michael Jacob

Person

Patents Grantslast 30 patents

Reducing memory failures in integrated circuits

Semiconductor device having semiconductor memory with sense amplifier

Memory cell signal window testing apparatus

Reducing effects of noise coupling in integrated circuits with memo...

Semiconductor device having semiconductor memory with sense amplifier

Sensing test circuit

2T2C signal margin test mode using a defined charge exchange betwee...

Ferroelectric memory integrated circuit with improved reliability

Memory integrated circuit

Variable capacitances for memory cells within a cell group

2T2C signal margin test mode using resistive element

Memory architecture with memory cell groups

Historical information storage for integrated circuits

Memory architecture

Patents Applicationslast 30 patents

Semiconductor device having semiconductor memory with sense amplifier

Signal margin test mode for FeRAM with ferroelectric reference capa...

Reference circuit implemented to reduce the degradation of referenc...

High density flash memory with high speed cache data interface

Memory cell signal window testing apparatus

Reducing effects of noise coupling in integrated circuits with memo...

2T2C signal margin test mode using a defined charge exchange betwee...

2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT

2T2C signal margin test mode using different pre-charge levels for...

Ferroelectric memory architecture

Semiconductor device having semiconductor memory with sense amplifier

HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS

MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS

Sensing test circuit

Memory integrated circuit

Variable capacitances for memory cells within a cell group

Ferroelectric memory integrated circuit with improved reliability

Reducing Memory Failures in Integrated Circuits