Michael John Shay

Person

Arlington, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power management circuit that qualifies powergood disposal signal
- Patent number 6,397,338
- Issue date May 28, 2002
- National Semiconductor Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management system with programable configuration circuitry us...
- Patent number 6,367,021
- Issue date Apr 2, 2002
- National Semiconductor Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor channel width and slew rate correction circuit and method
- Patent number 6,255,874
- Issue date Jul 3, 2001
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock enable/disable circuit of power management system
- Patent number 6,021,501
- Issue date Feb 1, 2000
- National Semiconductor Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal source clock generation circuit for use with power managem...
- Patent number 6,016,071
- Issue date Jan 18, 2000
- National Semiconductor Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management system that one of plurality of peripheral signals...
- Patent number 5,983,014
- Issue date Nov 9, 1999
- National Semiconductor Corp.
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock frequency change circuit
- Patent number 5,926,641
- Issue date Jul 20, 1999
- National Semiconductor Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display controller capable of accessing an external memory for gray...
- Patent number 5,900,886
- Issue date May 4, 1999
- National Semiconductor Corporation
- Michael John Shay
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Clock generation circuit for a display controller having a fine tun...
- Patent number 5,821,910
- Issue date Oct 13, 1998
- National Semiconductor Corporation
- Michael John Shay
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Configurable power management system having a clock stabilization f...
- Patent number 5,805,923
- Issue date Sep 8, 1998
- Sony Corporation
- Michael John Shay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supply and interface configurable input/output buffer
- Patent number 5,798,659
- Issue date Aug 25, 1998
- National Semiconductor Corporation
- Michael John Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with multiple functions sharing multiple interna...
- Patent number 5,774,684
- Issue date Jun 30, 1998
- National Semiconductor Corporation
- Ralph Warren Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supply and interface configurable input/output buffer
- Patent number 5,612,637
- Issue date Mar 18, 1997
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable distributed personal security
- Patent number 5,533,123
- Issue date Jul 2, 1996
- National Semiconductor Corporation
- Gordon Force
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage level triggered ESD protection circuit
- Patent number 5,508,649
- Issue date Apr 16, 1996
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tristate driver for interfacing to a bus subject to overvoltage con...
- Patent number 5,450,025
- Issue date Sep 12, 1995
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Overvoltage protection against charge leakage in an output driver
- Patent number 5,387,826
- Issue date Feb 7, 1995
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-disabling power-up detection circuit
- Patent number 5,323,067
- Issue date Jun 21, 1994
- National Semiconductor Corporation
- Michael J. Shay
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
POWER MANAGEMENT CIRCUIT THAT QUALIFIES POWERGOOD DISABLE SIGNAL
- Publication number 20010007113
- Publication date Jul 5, 2001
- MICHAEL JOHN SHAY
- G06 - COMPUTING CALCULATING COUNTING

Michael John Shay

Person

Patents Grantslast 30 patents

Power management circuit that qualifies powergood disposal signal

Power management system with programable configuration circuitry us...

Transistor channel width and slew rate correction circuit and method

Clock enable/disable circuit of power management system

Internal source clock generation circuit for use with power managem...

Power management system that one of plurality of peripheral signals...

Clock frequency change circuit

Display controller capable of accessing an external memory for gray...

Clock generation circuit for a display controller having a fine tun...

Configurable power management system having a clock stabilization f...

Supply and interface configurable input/output buffer

Integrated circuit with multiple functions sharing multiple interna...

Supply and interface configurable input/output buffer

Programmable distributed personal security

Voltage level triggered ESD protection circuit

Tristate driver for interfacing to a bus subject to overvoltage con...

Overvoltage protection against charge leakage in an output driver

Self-disabling power-up detection circuit

Patents Applicationslast 30 patents

POWER MANAGEMENT CIRCUIT THAT QUALIFIES POWERGOOD DISABLE SIGNAL