Michael K. Dugan

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Control parameter address virtualization
- Patent number 12,039,201
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing index update messages for memory-based communication queues
- Patent number 12,008,243
- Issue date Jun 11, 2024
- Micron Technology, Inc.
- Michael Keith Dugan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 11,550,719
- Issue date Jan 10, 2023
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 10,949,347
- Issue date Mar 16, 2021
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 10,061,699
- Issue date Aug 28, 2018
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,824,010
- Issue date Nov 21, 2017
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,449,659
- Issue date Sep 20, 2016
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,015,399
- Issue date Apr 21, 2015
- Convey Computer
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for scheduling memory requests utilizing multi-...
- Patent number 7,366,854
- Issue date Apr 29, 2008
- Hewlett-Packard Development Company, L.P.
- John M. Wastlick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for router packet control and ordering
- Patent number 6,876,657
- Issue date Apr 5, 2005
- Chiaro Networks, Ltd.
- Tony M. Brewer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for performing speculative cache directory tag...
- Patent number 6,564,306
- Issue date May 13, 2003
- Hewlett-Packard Development Company, L.P.
- Michael K Dugan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory error correction using redundant sliced memory and standard...
- Patent number 6,397,365
- Issue date May 28, 2002
- Hewlett-Packard Company
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REDUCING INDEX UPDATE MESSAGES FOR MEMORY-BASED COMMUNICATION QUEUES
- Publication number 20240143184
- Publication date May 2, 2024
- Micron Technology, Inc.
- Michael Keith Dugan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS REQUEST REORDERING ACROSS A MULTIPLE-CHANNEL INTERFACE FOR M...
- Publication number 20240069795
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Michael Keith Dugan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL PARAMETER ADDRESS VIRTUALIZATION
- Publication number 20240069804
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS REQUEST REORDERING FOR MEMORY-BASED COMMUNICATION QUEUES
- Publication number 20240069805
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Michael Keith Dugan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS
- Publication number 20240028390
- Publication date Jan 25, 2024
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20210182195
- Publication date Jun 17, 2021
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20180322054
- Publication date Nov 8, 2018
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20180060234
- Publication date Mar 1, 2018
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20160371185
- Publication date Dec 22, 2016
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20150206561
- Publication date Jul 23, 2015
- Convey Computer
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20100036997
- Publication date Feb 11, 2010
- Convey Computer
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Achieving Cache Coherency Within Multiprocess...
- Publication number 20080270708
- Publication date Oct 30, 2008
- Craig Warner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for scheduling memory requests utilizing multi-...
- Publication number 20040225847
- Publication date Nov 11, 2004
- John M. Wastlick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for performing speculative cache directory tag...
- Publication number 20010034815
- Publication date Oct 25, 2001
- Michael K. Dugan
- G06 - COMPUTING CALCULATING COUNTING

Michael K. Dugan

Person

Patents Grantslast 30 patents

Control parameter address virtualization

Reducing index update messages for memory-based communication queues

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Systems and methods for scheduling memory requests utilizing multi-...

System and method for router packet control and ordering

Apparatus and method for performing speculative cache directory tag...

Memory error correction using redundant sliced memory and standard...

Patents Applicationslast 30 patents

REDUCING INDEX UPDATE MESSAGES FOR MEMORY-BASED COMMUNICATION QUEUES

ACCESS REQUEST REORDERING ACROSS A MULTIPLE-CHANNEL INTERFACE FOR M...

CONTROL PARAMETER ADDRESS VIRTUALIZATION

ACCESS REQUEST REORDERING FOR MEMORY-BASED COMMUNICATION QUEUES

METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

System and Method for Achieving Cache Coherency Within Multiprocess...

Systems and methods for scheduling memory requests utilizing multi-...

Apparatus and method for performing speculative cache directory tag...