Michael Launsbach

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Level shifter for a time-varying input
- Patent number 9,312,858
- Issue date Apr 12, 2016
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level shifter for a time-varying input
- Patent number 9,287,873
- Issue date Mar 15, 2016
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Partial update in a ternary content addressable memory
- Patent number 9,218,880
- Issue date Dec 22, 2015
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated decoupling capacitor utilizing through-silicon via
- Patent number 9,196,671
- Issue date Nov 24, 2015
- International Business Machines Corporation
- Derick G. Behrends
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated decoupling capacitor utilizing through-silicon via
- Patent number 9,153,638
- Issue date Oct 6, 2015
- International Business Machines Corporation
- Derick G. Behrends
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout to minimize FET variation in small dimension photolithography
- Patent number 9,142,560
- Issue date Sep 22, 2015
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial update in a ternary content addressable memory
- Patent number 9,082,484
- Issue date Jul 14, 2015
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management SRAM write bit line drive circuit
- Patent number 9,058,861
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout to minimize FET variation in small dimension photolithography
- Patent number 8,860,141
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management domino SRAM bit line discharge circuit
- Patent number 8,842,487
- Issue date Sep 23, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Single cycle data copy for two-port SRAM
- Patent number 8,824,196
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data security for dynamic random access memory using body bias to c...
- Patent number 8,711,606
- Issue date Apr 29, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing RC and coupling delay correction for SRAM
- Patent number 8,675,427
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing power saving self powering down latch structure
- Patent number 8,669,800
- Issue date Mar 11, 2014
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementing mulitple mask lithography timing variation mitigation
- Patent number 8,578,304
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Data dependent SRAM write assist
- Patent number 8,520,429
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Data security for dynamic random access memory using body bias to c...
- Patent number 8,467,230
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Precise time period measurement
- Patent number 6,944,099
- Issue date Sep 13, 2005
- International Business Machines Corporation
- Curtis Walter Preuss
- G04 - HOROLOGY
Information Patent Grant
Dual mode analog differential and CMOS logic circuit
- Patent number 6,933,743
- Issue date Aug 23, 2005
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
LEVEL SHIFTER FOR A TIME-VARYING INPUT
- Publication number 20150349778
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL SHIFTER FOR A TIME-VARYING INPUT
- Publication number 20150349779
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY
- Publication number 20150179262
- Publication date Jun 25, 2015
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY
- Publication number 20150179261
- Publication date Jun 25, 2015
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
- Publication number 20140353764
- Publication date Dec 4, 2014
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGEMENT OF SRAM INITIALIZATION
- Publication number 20140293679
- Publication date Oct 2, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT
- Publication number 20140169076
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT
- Publication number 20140126276
- Publication date May 8, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA
- Publication number 20140127875
- Publication date May 8, 2014
- International Business Machines Corporation
- Derick G. Behrends
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT
- Publication number 20140126273
- Publication date May 8, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA
- Publication number 20140124943
- Publication date May 8, 2014
- International Business Machines Corporation
- Derick G. Behrends
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
- Publication number 20140092672
- Publication date Apr 3, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
- Publication number 20140092696
- Publication date Apr 3, 2014
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Single Cycle Data Copy for Two-Port SRAM
- Publication number 20130258758
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM
- Publication number 20130235681
- Publication date Sep 12, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE
- Publication number 20130222031
- Publication date Aug 29, 2013
- International Business Machines Corporation
- Derick G. Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
- Publication number 20130175631
- Publication date Jul 11, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...
- Publication number 20130148454
- Publication date Jun 13, 2013
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Data Dependent SRAM Write Assist
- Publication number 20120281457
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...
- Publication number 20120087176
- Publication date Apr 12, 2012
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Insulin Pump Having Expected Bolus Interval and an Early Bolus Inte...
- Publication number 20090005726
- Publication date Jan 1, 2009
- Steven Paul Jones
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
DUAL MODE ANALOG DIFFERENTIAL AND CMOS LOGIC CIRCUIT
- Publication number 20050110521
- Publication date May 26, 2005
- International Business Machines Corporation
- Delbert R. Cecchi
- H03 - BASIC ELECTRONIC CIRCUITRY

Michael Launsbach

Person

Patents Grantslast 30 patents

Level shifter for a time-varying input

Level shifter for a time-varying input

Partial update in a ternary content addressable memory

Integrated decoupling capacitor utilizing through-silicon via

Integrated decoupling capacitor utilizing through-silicon via

Layout to minimize FET variation in small dimension photolithography

Partial update in a ternary content addressable memory

Power management SRAM write bit line drive circuit

Layout to minimize FET variation in small dimension photolithography

Power management domino SRAM bit line discharge circuit

Single cycle data copy for two-port SRAM

Data security for dynamic random access memory using body bias to c...

Implementing RC and coupling delay correction for SRAM

Implementing power saving self powering down latch structure

Implementing mulitple mask lithography timing variation mitigation

Data dependent SRAM write assist

Data security for dynamic random access memory using body bias to c...

Precise time period measurement

Dual mode analog differential and CMOS logic circuit

Patents Applicationslast 30 patents

LEVEL SHIFTER FOR A TIME-VARYING INPUT

LEVEL SHIFTER FOR A TIME-VARYING INPUT

PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY

PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY

LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY

MANAGEMENT OF SRAM INITIALIZATION

POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT

POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT

INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA

POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT

INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA

POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT

POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT

Single Cycle Data Copy for Two-Port SRAM

IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM

IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE

LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...

Data Dependent SRAM Write Assist

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO C...

Insulin Pump Having Expected Bolus Interval and an Early Bolus Inte...

DUAL MODE ANALOG DIFFERENTIAL AND CMOS LOGIC CIRCUIT