Michael N. Derr

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
IPS SOC PLL monitoring and error reporting
- Patent number 11,544,160
- Issue date Jan 3, 2023
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically changing display clock frequency
- Patent number 11,158,292
- Issue date Oct 26, 2021
- Intel Corporation
- Prashant Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Video bandwidth optimization for multi-monitor systems
- Patent number 11,043,158
- Issue date Jun 22, 2021
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional safety system error injection technology
- Patent number 10,824,529
- Issue date Nov 3, 2020
- Intel Corporation
- Prashant Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detector and/or corrector checker method and apparatus
- Patent number 10,749,547
- Issue date Aug 18, 2020
- Intel Corporation
- Prashant D. Chaudhari
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Error reporting and handling using a common error handler
- Patent number 10,678,623
- Issue date Jun 9, 2020
- Intel Corporation
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for end-to-end display integrity verification for func...
- Patent number 10,643,573
- Issue date May 5, 2020
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-tolerant graphics display engine
- Patent number 10,387,993
- Issue date Aug 20, 2019
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling reduced power states using platform latency tolerance
- Patent number 9,541,983
- Issue date Jan 10, 2017
- Intel Corporation
- Barnes Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing power between domains in a processor package using encoded...
- Patent number 9,423,858
- Issue date Aug 23, 2016
- Intel Corporation
- Xiuting C. Mann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Controlling reduced power states using platform latency tolerance
- Patent number 9,195,292
- Issue date Nov 24, 2015
- Intel Corporation
- Barnes Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing cross-domain thermal control in a processor
- Patent number 9,189,046
- Issue date Nov 17, 2015
- Intel Corporation
- Xiuting C. Man
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Performing cross-domain thermal control in a processor
- Patent number 9,063,727
- Issue date Jun 23, 2015
- Intel Corporation
- Xiuting C. Man
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Determination of wake signal initiation on shared wake pins in comp...
- Patent number 9,032,225
- Issue date May 12, 2015
- Intel Corporation
- Christopher J. Lake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for determining an interface during a...
- Patent number 8,583,948
- Issue date Nov 12, 2013
- Intel Corporation
- Christopher J. Lake
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Mechanism for a shared serial peripheral interface
- Patent number 8,463,968
- Issue date Jun 11, 2013
- Intel Corporation
- Amir Zinaty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-optimized frame synchronization for multiple USB controllers...
- Patent number 8,347,015
- Issue date Jan 1, 2013
- Intel Corporation
- Michael N. Derr
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power-optimized frame synchronization for multiple USB controllers...
- Patent number 8,069,294
- Issue date Nov 29, 2011
- Intel Corporation
- Michael N. Derr
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Tri-layered power scheme for architectures which contain a micro-co...
- Patent number 7,900,072
- Issue date Mar 1, 2011
- Intel Corporation
- Michael Berger
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Quiescing a manageability engine
- Patent number 7,822,978
- Issue date Oct 26, 2010
- Intel Corporation
- David W. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chipset configuration authentication via manageability engine
- Patent number 7,712,145
- Issue date May 4, 2010
- Intel Corporation
- Kah Meng Yeem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-granular writes of control registers
- Patent number 7,694,004
- Issue date Apr 6, 2010
- Intel Corporation
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable feature selection mechanism
- Patent number 7,636,795
- Issue date Dec 22, 2009
- Intel Corporation
- Gary M. Hess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of coherent data transfer during processor idle s...
- Patent number 7,523,327
- Issue date Apr 21, 2009
- Intel Corporation
- Leslie E. Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
USB schedule prefetcher for low power
- Patent number 7,340,550
- Issue date Mar 4, 2008
- Intel Corporation
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for using a patch module to process non-posted re...
- Patent number 7,296,101
- Issue date Nov 13, 2007
- Intel Corporation
- Chee Siong Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting an interruption in memory initia...
- Patent number 7,093,115
- Issue date Aug 15, 2006
- Intel Corporation
- David I. Poisner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streamlining ATA device initialization
- Patent number 6,957,280
- Issue date Oct 18, 2005
- Intel Corporation
- Michael K. Eschmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streamlining ATA device initialization
- Patent number 6,779,062
- Issue date Aug 17, 2004
- Intel Corporation
- Michael K. Eschmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus communication
- Patent number 6,775,282
- Issue date Aug 10, 2004
- Intel Corporation
- Ramamohan R. Vakkalagadda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
GRANULAR GPU DVFS WITH EXECUTION UNIT PARTIAL POWERDOWN
- Publication number 20230334613
- Publication date Oct 19, 2023
- Intel Corporation
- Kenneth Daxer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRANULAR GPU DVFS WITH EXECUTION UNIT PARTIAL POWERDOWN
- Publication number 20230297159
- Publication date Sep 21, 2023
- Intel Corporation
- Kenneth Daxer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY CHANGING DISPLAY CLOCK FREQUENCY
- Publication number 20210233501
- Publication date Jul 29, 2021
- Intel Corporation
- Prashant Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO AVOID VISUAL ARTIFACTS IN A DISPLAY DEVICE...
- Publication number 20200312271
- Publication date Oct 1, 2020
- Intel Corporation
- Michael N. Derr
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
IPS SOC PLL MONITORING AND ERROR REPORTING
- Publication number 20200117554
- Publication date Apr 16, 2020
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT-TOLERANT GRAPHICS DISPLAY ENGINE
- Publication number 20190102861
- Publication date Apr 4, 2019
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR END-TO-END DISPLAY INTEGRITY VERIFICATION FOR FUNC...
- Publication number 20190051266
- Publication date Feb 14, 2019
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL SAFETY ERROR REPORTING AND HANDLING INFRASTRUCTURE
- Publication number 20190050279
- Publication date Feb 14, 2019
- Intel Corporation
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR DETECTOR AND/OR CORRECTOR CHECKER METHOD AND APPARATUS
- Publication number 20190052286
- Publication date Feb 14, 2019
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL SAFETY SYSTEM ERROR INJECTION TECHNOLOGY
- Publication number 20190050308
- Publication date Feb 14, 2019
- Intel Corporation
- Prashant Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIDEO BANDWIDTH OPTIMIZATION FOR MULTI-MONITOR SYSTEMS
- Publication number 20190043411
- Publication date Feb 7, 2019
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Reduced Power States Using Platform Latency Tolerance
- Publication number 20160041595
- Publication date Feb 11, 2016
- Intel Corporation
- Barnes Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Reduced Power States Using Platform Latency Tolerance
- Publication number 20150006923
- Publication date Jan 1, 2015
- Barnes Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE TO ALIGN AUDIO FLOW
- Publication number 20140180457
- Publication date Jun 26, 2014
- Anshuman Thakur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sharing Power Between Domains In A Processor Package
- Publication number 20140089688
- Publication date Mar 27, 2014
- Xiuting C. Man
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Cross-Domain Thermal Control In A Processor
- Publication number 20140068291
- Publication date Mar 6, 2014
- XIUTING C. MAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Cross-Domain Thermal Control In A Processor
- Publication number 20140068293
- Publication date Mar 6, 2014
- Xiuting C. Man
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZATION OF SHARED WAKE PINS IN COMPUTING DEVICES
- Publication number 20130339758
- Publication date Dec 19, 2013
- Christopher J. Lake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR DETERMINING AN INTERFACE DURING A...
- Publication number 20130007476
- Publication date Jan 3, 2013
- Christopher J. Lake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS...
- Publication number 20120072636
- Publication date Mar 22, 2012
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System And Method of Coherent Data Transfer During Processor Idle S...
- Publication number 20090193274
- Publication date Jul 30, 2009
- Intel Corporation
- Leslie E. Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRI-LAYERED POWER SCHEME FOR ARCHITECTURES WHICH CONTAIN A MICRO-CO...
- Publication number 20090164819
- Publication date Jun 25, 2009
- Michael Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chipset configuration authentication via manageability engine
- Publication number 20070234433
- Publication date Oct 4, 2007
- Kah Meng Yeem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power-optimized frame synchronization for multiple USB controllers...
- Publication number 20070233909
- Publication date Oct 4, 2007
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quiescing a processor bus agent
- Publication number 20070033311
- Publication date Feb 8, 2007
- David W. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for a shared serial peripheral interface
- Publication number 20060224803
- Publication date Oct 5, 2006
- Amir Zinaty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of coherent data transfer during processor idle s...
- Publication number 20060200690
- Publication date Sep 7, 2006
- Intel Corporation
- Leslie E. Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USB schedule prefetcher for low power
- Publication number 20060123180
- Publication date Jun 8, 2006
- Michael N. Derr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable feature selection mechanism
- Publication number 20060004928
- Publication date Jan 5, 2006
- Gary M. Hess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single instruction type based hardware patch controller
- Publication number 20050223292
- Publication date Oct 6, 2005
- Chee Siong Lee
- G06 - COMPUTING CALCULATING COUNTING

Michael N. Derr

Person

Patents Grantslast 30 patents

IPS SOC PLL monitoring and error reporting

Method and apparatus for dynamically changing display clock frequency

Video bandwidth optimization for multi-monitor systems

Functional safety system error injection technology

Error detector and/or corrector checker method and apparatus

Error reporting and handling using a common error handler

Technologies for end-to-end display integrity verification for func...

Fault-tolerant graphics display engine

Controlling reduced power states using platform latency tolerance

Sharing power between domains in a processor package using encoded...

Controlling reduced power states using platform latency tolerance

Performing cross-domain thermal control in a processor

Performing cross-domain thermal control in a processor

Determination of wake signal initiation on shared wake pins in comp...

Method, apparatus and system for determining an interface during a...

Mechanism for a shared serial peripheral interface

Power-optimized frame synchronization for multiple USB controllers...

Power-optimized frame synchronization for multiple USB controllers...

Tri-layered power scheme for architectures which contain a micro-co...

Quiescing a manageability engine

Chipset configuration authentication via manageability engine

Bit-granular writes of control registers

Configurable feature selection mechanism

System and method of coherent data transfer during processor idle s...

USB schedule prefetcher for low power

Method and system for using a patch module to process non-posted re...

Method and apparatus for detecting an interruption in memory initia...

Streamlining ATA device initialization

Streamlining ATA device initialization

Bus communication

Patents Applicationslast 30 patents

GRANULAR GPU DVFS WITH EXECUTION UNIT PARTIAL POWERDOWN

GRANULAR GPU DVFS WITH EXECUTION UNIT PARTIAL POWERDOWN

METHOD AND APPARATUS FOR DYNAMICALLY CHANGING DISPLAY CLOCK FREQUENCY

METHOD AND APPARATUS TO AVOID VISUAL ARTIFACTS IN A DISPLAY DEVICE...

IPS SOC PLL MONITORING AND ERROR REPORTING

FAULT-TOLERANT GRAPHICS DISPLAY ENGINE

TECHNOLOGIES FOR END-TO-END DISPLAY INTEGRITY VERIFICATION FOR FUNC...

FUNCTIONAL SAFETY ERROR REPORTING AND HANDLING INFRASTRUCTURE

ERROR DETECTOR AND/OR CORRECTOR CHECKER METHOD AND APPARATUS

FUNCTIONAL SAFETY SYSTEM ERROR INJECTION TECHNOLOGY

VIDEO BANDWIDTH OPTIMIZATION FOR MULTI-MONITOR SYSTEMS

Controlling Reduced Power States Using Platform Latency Tolerance

Controlling Reduced Power States Using Platform Latency Tolerance

ELECTRONIC DEVICE TO ALIGN AUDIO FLOW

Sharing Power Between Domains In A Processor Package

Performing Cross-Domain Thermal Control In A Processor

Performing Cross-Domain Thermal Control In A Processor

UTILIZATION OF SHARED WAKE PINS IN COMPUTING DEVICES

METHOD, APPARATUS AND SYSTEM FOR DETERMINING AN INTERFACE DURING A...

POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS...

System And Method of Coherent Data Transfer During Processor Idle S...

TRI-LAYERED POWER SCHEME FOR ARCHITECTURES WHICH CONTAIN A MICRO-CO...

Chipset configuration authentication via manageability engine

Power-optimized frame synchronization for multiple USB controllers...

Quiescing a processor bus agent

Mechanism for a shared serial peripheral interface

System and method of coherent data transfer during processor idle s...

USB schedule prefetcher for low power

Configurable feature selection mechanism

Single instruction type based hardware patch controller