Michael R. Seningen

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
System control using sparse data
- Patent number 12,072,810
- Issue date Aug 27, 2024
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data pattern based cache management
- Patent number 12,066,938
- Issue date Aug 20, 2024
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System control using sparse data
- Patent number 11,803,480
- Issue date Oct 31, 2023
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data pattern based cache management
- Patent number 11,755,480
- Issue date Sep 12, 2023
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data pattern based cache management
- Patent number 11,442,855
- Issue date Sep 13, 2022
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System control using sparse data
- Patent number 11,327,896
- Issue date May 10, 2022
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shifter with isolation on both input and output domains with...
- Patent number 10,838,483
- Issue date Nov 17, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output signal control during retention mode operation
- Patent number 10,812,081
- Issue date Oct 20, 2020
- Apple Inc.
- Michael R. Seningen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System control using sparse data
- Patent number 10,691,610
- Issue date Jun 23, 2020
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flop circuit with integrated clock gating circuit
- Patent number 10,491,197
- Issue date Nov 26, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock gating circuit
- Patent number 10,461,747
- Issue date Oct 29, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power detection circuit
- Patent number 10,191,086
- Issue date Jan 29, 2019
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Grant
Level shifting circuit with data resolution and grounded input nodes
- Patent number 10,187,061
- Issue date Jan 22, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transistor work function adjustment by laser stimulation
- Patent number 10,177,051
- Issue date Jan 8, 2019
- Apple Inc.
- Michael R. Seningen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Reduced power set-reset latch based flip-flop
- Patent number 10,033,356
- Issue date Jul 24, 2018
- Apple Inc.
- Zhao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transistor work function adjustment by laser stimulation
- Patent number 10,008,423
- Issue date Jun 26, 2018
- Apple Inc.
- Michael R. Seningen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Mode based skew to reduce scan instantaneous voltage drop and peak...
- Patent number 9,488,692
- Issue date Nov 8, 2016
- Apple Inc.
- Asad A. Bawa
- G01 - MEASURING TESTING
Information Patent Grant
On-die system for monitoring and predicting performance
- Patent number 9,453,879
- Issue date Sep 27, 2016
- Apple Inc.
- Brian S. Leibowitz
- G01 - MEASURING TESTING
Information Patent Grant
Weak bit detection using on-die voltage modulation
- Patent number 9,412,469
- Issue date Aug 9, 2016
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Goal-driven search of a stochastic process using reduced sets of si...
- Patent number 9,201,993
- Issue date Dec 1, 2015
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with bit line capacitive loading
- Patent number 9,177,671
- Issue date Nov 3, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with bit line current injection
- Patent number 9,076,556
- Issue date Jul 7, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with redundant sense amplifier
- Patent number 9,013,933
- Issue date Apr 21, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit slice elements utilizing through device routing
- Patent number 8,966,429
- Issue date Feb 24, 2015
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with variable strength sense amplifier
- Patent number 8,953,395
- Issue date Feb 10, 2015
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch array utilizing through device connectivity
- Patent number 8,947,120
- Issue date Feb 3, 2015
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weak bit detection in a memory through variable development time
- Patent number 8,780,654
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with bit line current injection
- Patent number 8,780,657
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with redundant sense amplifier
- Patent number 8,780,650
- Issue date Jul 15, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Data Pattern Based Cache Management
- Publication number 20250013568
- Publication date Jan 9, 2025
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Control Using Sparse Data
- Publication number 20250013576
- Publication date Jan 9, 2025
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Chain Analysis Using Predefined Capture Signature
- Publication number 20240393394
- Publication date Nov 28, 2024
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
Data Pattern Based Cache Management
- Publication number 20240232077
- Publication date Jul 11, 2024
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Pattern Based Cache Management
- Publication number 20240134792
- Publication date Apr 25, 2024
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Control Using Sparse Data
- Publication number 20240111685
- Publication date Apr 4, 2024
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Pattern Based Cache Management
- Publication number 20220414009
- Publication date Dec 29, 2022
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Control Using Sparse Data
- Publication number 20220269617
- Publication date Aug 25, 2022
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Bit Cell for In-Memory Computation
- Publication number 20220101914
- Publication date Mar 31, 2022
- Apple Inc.
- Michael A. Dreesen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Pattern Based Cache Management
- Publication number 20220100655
- Publication date Mar 31, 2022
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Control Using Sparse Data
- Publication number 20200320013
- Publication date Oct 8, 2020
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...
- Publication number 20200103957
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CONTROL USING SPARSE DATA
- Publication number 20190095339
- Publication date Mar 28, 2019
- Apple Inc.
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flop Circuit with Integrated Clock Gating Circuit
- Publication number 20190089337
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Power Clock Gating Circuit
- Publication number 20190089354
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSISTOR WORK FUNCTION ADJUSTMENT BY LASER STIMULATION
- Publication number 20180308772
- Publication date Oct 25, 2018
- Apple Inc.
- Michael R. Seningen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP
- Publication number 20170366170
- Publication date Dec 21, 2017
- Apple Inc.
- Zhao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER DETECTION CIRCUIT
- Publication number 20170276705
- Publication date Sep 28, 2017
- Apple Inc.
- Michael R. Seningen
- G01 - MEASURING TESTING
Information Patent Application
WEAK BIT DETECTION USING ON-DIE VOLTAGE MODULATION
- Publication number 20160240266
- Publication date Aug 18, 2016
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
ON-DIE SYSTEM FOR MONITORING AND PREDICTING PERFORMANCE
- Publication number 20160154055
- Publication date Jun 2, 2016
- Apple Inc.
- Brian S. Leibowitz
- G01 - MEASURING TESTING
Information Patent Application
Mode Based Skew to Reduce Scan Instantaneous Voltage Drop and Peak...
- Publication number 20160061889
- Publication date Mar 3, 2016
- Apple Inc.
- Asad A. Bawa
- G01 - MEASURING TESTING
Information Patent Application
LATCH CIRCUIT WITH DUAL-ENDED WRITE
- Publication number 20150207496
- Publication date Jul 23, 2015
- Apple Inc.
- Michael R Seningen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20140269025
- Publication date Sep 18, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH BIT LINE CURRENT INJECTION
- Publication number 20140269124
- Publication date Sep 18, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
POST MANUFACTURING STRAIN MANIPULATION IN SEMICONDUCTOR DEVICES
- Publication number 20140084234
- Publication date Mar 27, 2014
- Apple Inc.
- Michael R Seningen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATCH ARRAY UTILIZING THROUGH DEVICE CONNECTIVITY
- Publication number 20140070841
- Publication date Mar 13, 2014
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT SLICE ELEMENTS UTILIZING THROUGH DEVICE ROUTING
- Publication number 20140075401
- Publication date Mar 13, 2014
- Michael R. Seningen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20140010030
- Publication date Jan 9, 2014
- Apple Inc.
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
WEAK BIT DETECTION IN A MEMORY THROUGH VARIABLE DEVELOPMENT TIME
- Publication number 20130265836
- Publication date Oct 10, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH REDUNDANT SENSE AMPLIFIER
- Publication number 20130258790
- Publication date Oct 3, 2013
- Michael R. Seningen
- G11 - INFORMATION STORAGE

Michael R. Seningen

Person

Patents Grantslast 30 patents

Scan chain analysis using predefined capture signature

System control using sparse data

Data pattern based cache management

System control using sparse data

Data pattern based cache management

Data pattern based cache management

System control using sparse data

Level shifter with isolation on both input and output domains with...

Output signal control during retention mode operation

System control using sparse data

Flop circuit with integrated clock gating circuit

Low power clock gating circuit

Power detection circuit

Level shifting circuit with data resolution and grounded input nodes

Transistor work function adjustment by laser stimulation

Reduced power set-reset latch based flip-flop

Transistor work function adjustment by laser stimulation

Mode based skew to reduce scan instantaneous voltage drop and peak...

On-die system for monitoring and predicting performance

Weak bit detection using on-die voltage modulation

Goal-driven search of a stochastic process using reduced sets of si...

Memory with bit line capacitive loading

Memory with bit line current injection

Memory with redundant sense amplifier

Bit slice elements utilizing through device routing

Memory with variable strength sense amplifier

Latch array utilizing through device connectivity

Weak bit detection in a memory through variable development time

Memory with bit line current injection

Memory with redundant sense amplifier

Patents Applicationslast 30 patents

Data Pattern Based Cache Management

System Control Using Sparse Data

Scan Chain Analysis Using Predefined Capture Signature

Data Pattern Based Cache Management

Data Pattern Based Cache Management

System Control Using Sparse Data

Data Pattern Based Cache Management

System Control Using Sparse Data

Memory Bit Cell for In-Memory Computation

Data Pattern Based Cache Management

System Control Using Sparse Data

LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...

SYSTEM CONTROL USING SPARSE DATA

Flop Circuit with Integrated Clock Gating Circuit

Low Power Clock Gating Circuit

TRANSISTOR WORK FUNCTION ADJUSTMENT BY LASER STIMULATION

REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP

POWER DETECTION CIRCUIT

WEAK BIT DETECTION USING ON-DIE VOLTAGE MODULATION

ON-DIE SYSTEM FOR MONITORING AND PREDICTING PERFORMANCE

Mode Based Skew to Reduce Scan Instantaneous Voltage Drop and Peak...

LATCH CIRCUIT WITH DUAL-ENDED WRITE

MEMORY WITH REDUNDANT SENSE AMPLIFIER

MEMORY WITH BIT LINE CURRENT INJECTION

POST MANUFACTURING STRAIN MANIPULATION IN SEMICONDUCTOR DEVICES

LATCH ARRAY UTILIZING THROUGH DEVICE CONNECTIVITY

BIT SLICE ELEMENTS UTILIZING THROUGH DEVICE ROUTING

MEMORY WITH REDUNDANT SENSE AMPLIFIER

WEAK BIT DETECTION IN A MEMORY THROUGH VARIABLE DEVELOPMENT TIME

MEMORY WITH REDUNDANT SENSE AMPLIFIER