Michael R. Trocino

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,900,124
- Issue date Feb 13, 2024
- Coherent Logix, Incorporated
- Michael B Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 11,829,320
- Issue date Nov 28, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with improved secondary interconnection network
- Patent number 11,755,504
- Issue date Sep 12, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 11,550,750
- Issue date Jan 10, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,544,072
- Issue date Jan 3, 2023
- Coherent Logix, Inc.
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 11,030,023
- Issue date Jun 8, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 11,016,779
- Issue date May 25, 2021
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 10,838,787
- Issue date Nov 17, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with improved secondary interconnection network
- Patent number 10,747,689
- Issue date Aug 18, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory network processor
- Patent number 10,747,709
- Issue date Aug 18, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure boot sequence for selectively disabling configurable communi...
- Patent number 10,685,143
- Issue date Jun 16, 2020
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 10,521,285
- Issue date Dec 31, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with improved secondary interconnection network
- Patent number 10,185,672
- Issue date Jan 22, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 10,185,608
- Issue date Jan 22, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network for multi-frequency multi-processor systems
- Patent number 10,007,293
- Issue date Jun 26, 2018
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Secure boot sequence for selectively disabling configurable communi...
- Patent number 10,007,806
- Issue date Jun 26, 2018
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 9,990,241
- Issue date Jun 5, 2018
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 9,720,867
- Issue date Aug 1, 2017
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with improved secondary interconnection network
- Patent number 9,612,984
- Issue date Apr 4, 2017
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network for multi-frequency multi-processor systems
- Patent number 9,450,590
- Issue date Sep 20, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory-network processor with programmable optimizations
- Patent number 9,430,369
- Issue date Aug 30, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors with multi-layer int...
- Patent number 9,430,422
- Issue date Aug 30, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 9,424,213
- Issue date Aug 23, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multiprocessor fabric having configurable communication that is sel...
- Patent number 9,424,441
- Issue date Aug 23, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic selection of on-chip clock in synchronous digital systems
- Patent number 9,325,329
- Issue date Apr 26, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiprocessor system with improved secondary interconnection network
- Patent number 9,292,464
- Issue date Mar 22, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multi-frequency clock skew control for inter-chip communication in...
- Patent number 9,154,142
- Issue date Oct 6, 2015
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-frequency clock skew control for inter-chip communication in...
- Patent number 8,963,599
- Issue date Feb 24, 2015
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for disabling communication paths in a multiproce...
- Patent number 8,880,866
- Issue date Nov 4, 2014
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
- Publication number 20240256472
- Publication date Aug 1, 2024
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20230153117
- Publication date May 18, 2023
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20230061478
- Publication date Mar 2, 2023
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors DMA-FIFO
- Publication number 20210326193
- Publication date Oct 21, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20210208895
- Publication date Jul 8, 2021
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20210034566
- Publication date Feb 4, 2021
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
- Publication number 20200341914
- Publication date Oct 29, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selectively Disabling Configurable Communication Paths of a Multipr...
- Publication number 20200302090
- Publication date Sep 24, 2020
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INT...
- Publication number 20200117521
- Publication date Apr 16, 2020
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Network Processor with Programmable Optimizations
- Publication number 20190369990
- Publication date Dec 5, 2019
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiprocessor System with Improved Secondary Interconnection Network
- Publication number 20190155761
- Publication date May 23, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors With Multi-Layer Int...
- Publication number 20190155666
- Publication date May 23, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Network Processor
- Publication number 20190138492
- Publication date May 9, 2019
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Boot Sequence for Selectively Disabling Configurable Communi...
- Publication number 20180276416
- Publication date Sep 27, 2018
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors With Multi-Layer Int...
- Publication number 20180267846
- Publication date Sep 20, 2018
- Coherent Logix, Incorporated
- Carl S. Dobbs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Processing System With Interspersed Processors With Multi-Layer Int...
- Publication number 20170286196
- Publication date Oct 5, 2017
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
- Publication number 20170161214
- Publication date Jun 8, 2017
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS
- Publication number 20160370823
- Publication date Dec 22, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors DMA-FIFO
- Publication number 20160335207
- Publication date Nov 17, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing System With Interspersed Processors With Multi-Layer Int...
- Publication number 20160335218
- Publication date Nov 17, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20160328231
- Publication date Nov 10, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Boot Sequence for Selectively Disabling Configurable Communi...
- Publication number 20160232357
- Publication date Aug 11, 2016
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
- Publication number 20160162424
- Publication date Jun 9, 2016
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN...
- Publication number 20150162920
- Publication date Jun 11, 2015
- Coherent Logix, Incorporated
- Carl S. Dobbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multiprocessor Fabric Having Configurable Communication that is Sel...
- Publication number 20150026451
- Publication date Jan 22, 2015
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS
- Publication number 20140351551
- Publication date Nov 27, 2014
- Coherent Logix, Incorporated
- Michael B. Doerr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN...
- Publication number 20140167825
- Publication date Jun 19, 2014
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC SELECTION OF ON-CHIP CLOCK IN SYNCHRONOUS DIGITAL SYSTEMS
- Publication number 20140173324
- Publication date Jun 19, 2014
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS
- Publication number 20140173321
- Publication date Jun 19, 2014
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
- Publication number 20140173161
- Publication date Jun 19, 2014
- Coherent Logix, Incorporated
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING

Michael R. Trocino

Person

Patents Grantslast 30 patents

Memory-network processor with programmable optimizations

Memory network processor

Multiprocessor system with improved secondary interconnection network

Memory network processor

Memory-network processor with programmable optimizations

Processing system with interspersed processors DMA-FIFO

Memory-network processor with programmable optimizations

Processing system with interspersed processors with multi-layer int...

Multiprocessor system with improved secondary interconnection network

Memory network processor

Secure boot sequence for selectively disabling configurable communi...

Processing system with interspersed processors with multi-layer int...

Multiprocessor system with improved secondary interconnection network

Processing system with interspersed processors with multi-layer int...

Clock distribution network for multi-frequency multi-processor systems

Secure boot sequence for selectively disabling configurable communi...

Processing system with interspersed processors with multi-layer int...

Processing system with interspersed processors with multi-layer int...

Multiprocessor system with improved secondary interconnection network

Clock distribution network for multi-frequency multi-processor systems

Memory-network processor with programmable optimizations

Processing system with interspersed processors with multi-layer int...

Processing system with interspersed processors DMA-FIFO

Multiprocessor fabric having configurable communication that is sel...

Automatic selection of on-chip clock in synchronous digital systems

Multiprocessor system with improved secondary interconnection network

Multi-frequency clock skew control for inter-chip communication in...

Multi-frequency clock skew control for inter-chip communication in...

Method and system for disabling communication paths in a multiproce...

Patents Applicationslast 30 patents

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Memory Network Processor

Processing System With Interspersed Processors DMA-FIFO

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Memory Network Processor

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

Selectively Disabling Configurable Communication Paths of a Multipr...

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INT...

Memory-Network Processor with Programmable Optimizations

Multiprocessor System with Improved Secondary Interconnection Network

Processing System With Interspersed Processors With Multi-Layer Int...

Memory Network Processor

Secure Boot Sequence for Selectively Disabling Configurable Communi...

Processing System With Interspersed Processors With Multi-Layer Int...

Processing System With Interspersed Processors With Multi-Layer Int...

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS

Processing System With Interspersed Processors DMA-FIFO

Processing System With Interspersed Processors With Multi-Layer Int...

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

Secure Boot Sequence for Selectively Disabling Configurable Communi...

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN...

Multiprocessor Fabric Having Configurable Communication that is Sel...

MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS

MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN...

AUTOMATIC SELECTION OF ON-CHIP CLOCK IN SYNCHRONOUS DIGITAL SYSTEMS

CLOCK DISTRIBUTION NETWORK FOR MULTI-FREQUENCY MULTI-PROCESSOR SYSTEMS

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK