Michael R. Trombley

Person

Carey, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Digital signal processors providing scalable decision feedback equa...
- Patent number 11,838,153
- Issue date Dec 5, 2023
- Microsoft Technology Licensing, LLC
- Md Masum Hossain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic sequential approximation register (SAR) analog-to-digital c...
- Patent number 10,804,919
- Issue date Oct 13, 2020
- Microsoft Technology Licensing, LLC
- Hayden Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery broadcast for multi-lane SerDes
- Patent number 10,411,873
- Issue date Sep 10, 2019
- QUALCOMM Incorporated
- Brian Joel Schuh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing memory bandwidth compression in chipkill-correct memory a...
- Patent number 10,236,917
- Issue date Mar 19, 2019
- QUALCOMM Incorporated
- Natarajan Vaidhyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual in-line memory modules (DIMMs) supporting storage of a data in...
- Patent number 9,710,324
- Issue date Jul 18, 2017
- QUALCOMM Incorporated
- Michael Raymond Trombley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory access alignment in a double data rate (‘DDR’) system
- Patent number 9,436,388
- Issue date Sep 6, 2016
- International Business Machines Corporation
- Steven K. Jenkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access alignment in a double data rate (‘DDR’) system
- Patent number 9,343,123
- Issue date May 17, 2016
- International Business Machines Corporation
- Steven K. Jenkins
- G11 - INFORMATION STORAGE
Information Patent Grant
System for error decoding with retries and associated methods
- Patent number 9,128,868
- Issue date Sep 8, 2015
- International Business Machines Corporation
- Luis A. Lastras-Montano
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for handling data access
- Patent number 9,053,031
- Issue date Jun 9, 2015
- International Business Machines Corporation
- James Johnson Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access alignment in a double data rate (‘DDR’) system
- Patent number 8,902,683
- Issue date Dec 2, 2014
- International Business Machines Corporation
- Steven K. Jenkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access alignment in a double data rate (‘DDR’) system
- Patent number 8,547,760
- Issue date Oct 1, 2013
- International Business Machines Corporation
- Steven K. Jenkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correcting code protected quasi-static bit communication on a...
- Patent number 8,516,338
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Peter Buchmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascade interconnect memory system with enhanced reliability
- Patent number 8,245,105
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Timothy J. Dell
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correcting code protected quasi-static bit communication on a...
- Patent number 8,234,540
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Peter Buchmann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System to improve error correction using variable latency and assoc...
- Patent number 8,181,094
- Issue date May 15, 2012
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to improve miscorrection rates in error control code through...
- Patent number 8,176,391
- Issue date May 8, 2012
- International Business Machines Corporation
- Irving G. Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for selectively closing pages in a memory
- Patent number 8,140,825
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Ganesh Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for reducing latency associated with read operations in a...
- Patent number 8,140,803
- Issue date Mar 20, 2012
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on initialization and test for a cascade interconnect memory...
- Patent number 8,139,430
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Peter L. Buchmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Systems and methods for masking latency of memory reorganization wo...
- Patent number 8,122,216
- Issue date Feb 21, 2012
- International Business Machines Corporation
- David Michael Daly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program products for dynamic selecti...
- Patent number 8,099,570
- Issue date Jan 17, 2012
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for handling data access
- Patent number 8,032,713
- Issue date Oct 4, 2011
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for data bus bandwidth scheduling in an FBDIMM memory sys...
- Patent number 8,028,257
- Issue date Sep 27, 2011
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for handling data requests
- Patent number 7,949,830
- Issue date May 24, 2011
- International Business Machines Corporation
- James Johnson Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced bandwidth utilization
- Patent number 7,944,931
- Issue date May 17, 2011
- International Business Machines Corporation
- Brian M. Bass
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Structure for handling data requests
- Patent number 7,937,533
- Issue date May 3, 2011
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error control coding methods for memories with subline accesses
- Patent number 7,895,502
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Junsheng Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus bandwidth scheduling in an FBDIMM memory system operating...
- Patent number 7,660,952
- Issue date Feb 9, 2010
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing latency associated with read oper...
- Patent number 7,657,771
- Issue date Feb 2, 2010
- International Business Machines Corporation
- James J. Allen, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with apparatus and method to enable balanced bandwidt...
- Patent number 7,286,543
- Issue date Oct 23, 2007
- International Business Machines Corporation
- Brian M. Bass
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CLOCK DATA RECOVERY BROADCAST FOR MULTI-LANE SERDES
- Publication number 20190280849
- Publication date Sep 12, 2019
- QUALCOMM Incorporated
- Brian Joel SCHUH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT
- Publication number 20190087351
- Publication date Mar 21, 2019
- QUALCOMM Incorporated
- Sadayan Ghows Ghani Sadayan Ebramsah Mo ABDUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MEMORY BANDWIDTH COMPRESSION IN CHIPKILL-CORRECT MEMORY A...
- Publication number 20180074893
- Publication date Mar 15, 2018
- QUALCOMM Incorporated
- Natarajan Vaidhyanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MEMORY BANDWIDTH COMPRESSION USING BACK-TO-BACK READ OPER...
- Publication number 20160224241
- Publication date Aug 4, 2016
- QUALCOMM Incorporated
- Colin Beaton Verrilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL IN-LINE MEMORY MODULES (DIMMs) SUPPORTING STORAGE OF A DATA IN...
- Publication number 20160224414
- Publication date Aug 4, 2016
- QUALCOMM Incorporated
- Michael Raymond Trombley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM
- Publication number 20160216897
- Publication date Jul 28, 2016
- International Business Machines Corporation
- STEVEN K. JENKINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM
- Publication number 20140379979
- Publication date Dec 25, 2014
- STEVEN K. JENKINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM
- Publication number 20130346686
- Publication date Dec 26, 2013
- International Business Machines Corporation
- STEVEN K. JENKINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access Alignment In A Double Data Rate ('DDR') System
- Publication number 20130003475
- Publication date Jan 3, 2013
- International Business Machines Corporation
- Steven K. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A...
- Publication number 20120272119
- Publication date Oct 25, 2012
- Peter Buchmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Miscorrection Rates in Error Control Code Through...
- Publication number 20100299576
- Publication date Nov 25, 2010
- International Business Machines Corporation
- Irving G. Baysah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System to Improve Error Correction Using Variable Latency and Assoc...
- Publication number 20100293438
- Publication date Nov 18, 2010
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Error Decoding with Retries and Associated Methods
- Publication number 20100287436
- Publication date Nov 11, 2010
- International Business Machines Corporation
- Luis A. Lastras-Montano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Selectively Closing Pages in a Memory
- Publication number 20100037034
- Publication date Feb 11, 2010
- International Business Machines Corporation
- Ganesh Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM
- Publication number 20100005214
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Michael R. Trombley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY
- Publication number 20100005366
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Timothy J. Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC READ DATA FLOW CONTROL IN A CASCADE INTERCONNECT MEMORY S...
- Publication number 20100005206
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Steven J. Hnatko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A...
- Publication number 20100005365
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Peter Buchmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNEC...
- Publication number 20100005212
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Kevin C. Gower
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY...
- Publication number 20100005281
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Peter L. Buchmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arrangements for Operating In-Line Memory Module Configurations
- Publication number 20090276559
- Publication date Nov 5, 2009
- International Business Machines Corporation
- James J. Allen, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTI...
- Publication number 20090216985
- Publication date Aug 27, 2009
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR HANDLING DATA REQUESTS
- Publication number 20090150622
- Publication date Jun 11, 2009
- International Business Machines Corporation
- James Johnson Allen, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR HANDLING DATA ACCESS
- Publication number 20090150618
- Publication date Jun 11, 2009
- JAMES J. ALLEN, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR HANDLING DATA REQUESTS
- Publication number 20090150572
- Publication date Jun 11, 2009
- JAMES J. ALLEN, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR HANDLING DATA ACCESS
- Publication number 20090150401
- Publication date Jun 11, 2009
- International Business Machines Corporation
- James Johnson Allen, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDT...
- Publication number 20080240110
- Publication date Oct 2, 2008
- International Business Machines Corporation
- Brian M. Bass
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING...
- Publication number 20080215832
- Publication date Sep 4, 2008
- James J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYS...
- Publication number 20080215783
- Publication date Sep 4, 2008
- James J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A...
- Publication number 20080209095
- Publication date Aug 28, 2008
- JAMES J. ALLEN
- G06 - COMPUTING CALCULATING COUNTING

Michael R. Trombley

Person

Patents Grantslast 30 patents

Digital signal processors providing scalable decision feedback equa...

Dynamic sequential approximation register (SAR) analog-to-digital c...

Clock data recovery broadcast for multi-lane SerDes

Providing memory bandwidth compression in chipkill-correct memory a...

Dual in-line memory modules (DIMMs) supporting storage of a data in...

Memory access alignment in a double data rate (‘DDR’) system

Memory access alignment in a double data rate (‘DDR’) system

System for error decoding with retries and associated methods

System and method for handling data access

Memory access alignment in a double data rate (‘DDR’) system

Memory access alignment in a double data rate (‘DDR’) system

Error correcting code protected quasi-static bit communication on a...

Cascade interconnect memory system with enhanced reliability

Error correcting code protected quasi-static bit communication on a...

System to improve error correction using variable latency and assoc...

System to improve miscorrection rates in error control code through...

Systems and methods for selectively closing pages in a memory

Structure for reducing latency associated with read operations in a...

Power-on initialization and test for a cascade interconnect memory...

Systems and methods for masking latency of memory reorganization wo...

Methods, systems, and computer program products for dynamic selecti...

Structure for handling data access

Structure for data bus bandwidth scheduling in an FBDIMM memory sys...

System and method for handling data requests

Balanced bandwidth utilization

Structure for handling data requests

Error control coding methods for memories with subline accesses

Data bus bandwidth scheduling in an FBDIMM memory system operating...

Method and apparatus for reducing latency associated with read oper...

Memory system with apparatus and method to enable balanced bandwidt...

Patents Applicationslast 30 patents

CLOCK DATA RECOVERY BROADCAST FOR MULTI-LANE SERDES

TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT

PROVIDING MEMORY BANDWIDTH COMPRESSION IN CHIPKILL-CORRECT MEMORY A...

PROVIDING MEMORY BANDWIDTH COMPRESSION USING BACK-TO-BACK READ OPER...

DUAL IN-LINE MEMORY MODULES (DIMMs) SUPPORTING STORAGE OF A DATA IN...

MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM

MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM

MEMORY ACCESS ALIGNMENT IN A DOUBLE DATA RATE ('DDR') SYSTEM

Memory Access Alignment In A Double Data Rate ('DDR') System

ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A...

System to Improve Miscorrection Rates in Error Control Code Through...

System to Improve Error Correction Using Variable Latency and Assoc...

System for Error Decoding with Retries and Associated Methods

Systems and Methods for Selectively Closing Pages in a Memory

ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM

CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY

AUTOMATIC READ DATA FLOW CONTROL IN A CASCADE INTERCONNECT MEMORY S...

ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A...

PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNEC...

POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY...

Arrangements for Operating In-Line Memory Module Configurations

METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTI...

SYSTEM AND METHOD FOR HANDLING DATA REQUESTS

STRUCTURE FOR HANDLING DATA ACCESS

STRUCTURE FOR HANDLING DATA REQUESTS

SYSTEM AND METHOD FOR HANDLING DATA ACCESS

MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDT...

DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING...

STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYS...

STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A...