Michael Rennie

Person

Richmond, VA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Superconductor structure with normal metal connection to a resistor...
- Patent number 11,522,118
- Issue date Dec 6, 2022
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preclean and dielectric deposition methodology for superconductor i...
- Patent number 10,985,059
- Issue date Apr 20, 2021
- Northrop Grumman Systems Corporation
- Brian Paul Wagner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition methodology for superconductor interconnects
- Patent number 10,763,419
- Issue date Sep 1, 2020
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a superconductor device
- Patent number 10,608,159
- Issue date Mar 31, 2020
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming superconductor structures
- Patent number 10,312,142
- Issue date Jun 4, 2019
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preclean methodology for superconductor interconnect fabrication
- Patent number 10,312,141
- Issue date Jun 4, 2019
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preclean and deposition methodology for superconductor interconnects
- Patent number 10,276,504
- Issue date Apr 30, 2019
- Northrop Grumman Systems Corporation
- Vivien Luu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Superconductor device interconnect
- Patent number 10,158,062
- Issue date Dec 18, 2018
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Superconductor device interconnect
- Patent number 10,003,005
- Issue date Jun 19, 2018
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar junction transistor device having base epitaxy region on et...
- Patent number 9,812,445
- Issue date Nov 7, 2017
- Northrop Grumman Systems Corporation
- Patrick B. Shea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Superconductor device interconnect structure
- Patent number 9,780,285
- Issue date Oct 3, 2017
- Northrop Grumman Systems Corporation
- Christopher F. Kirby
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making bipolar junction transistor by forming base epitax...
- Patent number 9,142,546
- Issue date Sep 22, 2015
- Northrop Grumman Systems Corporation
- Patrick B. Shea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded capacitor and method of fabricating the same
- Patent number 8,551,856
- Issue date Oct 8, 2013
- Northrop Grumman Systems Corporation
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for integrating SONOS non-volatile memory into a sub-90 nm s...
- Patent number 8,409,950
- Issue date Apr 2, 2013
- Northrop Grumman Systems Corporation
- Patrick Bruckner Shea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a semiconductor device having deep trench s...
- Patent number 7,402,487
- Issue date Jul 22, 2008
- Infineon Technologies Richmond, LP
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Edge protection process for semiconductor device fabrication
- Patent number 7,208,326
- Issue date Apr 24, 2007
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a gate contact in a semiconductor device
- Patent number 6,927,462
- Issue date Aug 9, 2005
- Infineon Technologes Richmond, LP
- Francis Goodwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon corner rounding by ion implantation for shallow trench isol...
- Patent number 6,174,787
- Issue date Jan 16, 2001
- White Oak Semiconductor Partnership
- Robert Fuller
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUPERCONDUCTOR STRUCTURE WITH NORMAL METAL CONNECTION TO A RESISTOR...
- Publication number 20210217949
- Publication date Jul 15, 2021
- Northrop Grumman Systems Corporation
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRECLEAN AND DIELECTRIC DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR I...
- Publication number 20200144114
- Publication date May 7, 2020
- Northrop Grumman Systems Corporation
- BRIAN PAUL WAGNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECTS
- Publication number 20180351072
- Publication date Dec 6, 2018
- Northrop Grumman Systems Corporation
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRECLEAN AND DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECTS
- Publication number 20180337138
- Publication date Nov 22, 2018
- Northrop Grumman Systems Corporation
- VIVIEN LUU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPERCONDUCTOR DEVICE INTERCONNECT
- Publication number 20180301614
- Publication date Oct 18, 2018
- NORTHROP GRUMMAN SYSTEMS CORPORATION
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SUPERCONDUCTOR STRUCTURES
- Publication number 20180151430
- Publication date May 31, 2018
- Northrop Grumman Systems Corporation
- Christopher F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SUPERCONDUCTOR DEVICE
- Publication number 20180138389
- Publication date May 17, 2018
- Northrop Grumman Systems Corporation
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPERCONDUCTOR DEVICE INTERCONNECT
- Publication number 20180062061
- Publication date Mar 1, 2018
- Northrop Grumman Systems Corporation
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRECLEAN METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION
- Publication number 20180053689
- Publication date Feb 22, 2018
- Northrop Grumman Systems Corporation
- CHRISTOPHER F. KIRBY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR JUNCTION TRANSISTOR DEVICE HAVING BASE EPITAXY REGION ON ET...
- Publication number 20170309618
- Publication date Oct 26, 2017
- Northrop Grumman Systems Corporation
- PATRICK B. SHEA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME
- Publication number 20150357448
- Publication date Dec 10, 2015
- Northrop Grumman Systems Corporation
- PATRICK B. SHEA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME
- Publication number 20150162322
- Publication date Jun 11, 2015
- Northrop Grumman Systems Corporation
- PATRICK B. SHEA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED CAPACITOR AND METHOD OF FABRICATING THE SAME
- Publication number 20130075862
- Publication date Mar 28, 2013
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM on SOI
- Publication number 20060105519
- Publication date May 18, 2006
- Infineon Technologies Richmond, LP
- Jonathan Philip Davis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for fabricating a semiconductor device having deep trench s...
- Publication number 20060084222
- Publication date Apr 20, 2006
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge protection process for semiconductor device fabrication
- Publication number 20060084274
- Publication date Apr 20, 2006
- Infineon Technologies Richmond, LP
- Michael Rennie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a gate contact in a semiconductor device
- Publication number 20040043592
- Publication date Mar 4, 2004
- Infineon Technologies Richmond, LP
- Francis Goodwin
- H01 - BASIC ELECTRIC ELEMENTS

Michael Rennie

Person

Patents Grantslast 30 patents

Superconductor structure with normal metal connection to a resistor...

Preclean and dielectric deposition methodology for superconductor i...

Deposition methodology for superconductor interconnects

Method of making a superconductor device

Method of forming superconductor structures

Preclean methodology for superconductor interconnect fabrication

Preclean and deposition methodology for superconductor interconnects

Superconductor device interconnect

Superconductor device interconnect

Bipolar junction transistor device having base epitaxy region on et...

Superconductor device interconnect structure

Method of making bipolar junction transistor by forming base epitax...

Embedded capacitor and method of fabricating the same

Method for integrating SONOS non-volatile memory into a sub-90 nm s...

Process for fabricating a semiconductor device having deep trench s...

Edge protection process for semiconductor device fabrication

Method of forming a gate contact in a semiconductor device

Silicon corner rounding by ion implantation for shallow trench isol...

Patents Applicationslast 30 patents

SUPERCONDUCTOR STRUCTURE WITH NORMAL METAL CONNECTION TO A RESISTOR...

PRECLEAN AND DIELECTRIC DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR I...

DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECTS

PRECLEAN AND DEPOSITION METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECTS

SUPERCONDUCTOR DEVICE INTERCONNECT

METHOD OF FORMING SUPERCONDUCTOR STRUCTURES

METHOD OF MAKING A SUPERCONDUCTOR DEVICE

SUPERCONDUCTOR DEVICE INTERCONNECT

PRECLEAN METHODOLOGY FOR SUPERCONDUCTOR INTERCONNECT FABRICATION

BIPOLAR JUNCTION TRANSISTOR DEVICE HAVING BASE EPITAXY REGION ON ET...

BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME

BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME

EMBEDDED CAPACITOR AND METHOD OF FABRICATING THE SAME

DRAM on SOI

Process for fabricating a semiconductor device having deep trench s...

Edge protection process for semiconductor device fabrication

Method of forming a gate contact in a semiconductor device