Michael Rhodehamel

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Utilization based installation on a computing system
- Patent number 7,802,083
- Issue date Sep 21, 2010
- Intel Corporation
- Nagasubramanian Gurumoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number RE38388
- Issue date Jan 13, 2004
- Intel Corporation
- Nitin V. Sarangdhar
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 6,114,887
- Issue date Sep 5, 2000
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto-configuration support for multiple processor-ready pair or FRC...
- Patent number 6,061,599
- Issue date May 9, 2000
- Intel Corporation
- Michael W. Rhodehamel
- G05 - CONTROLLING REGULATING
Information Patent Grant
Control register bus access through a standardized test access port
- Patent number 6,055,656
- Issue date Apr 25, 2000
- Intel Corporation
- James A. Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus agent providing dynamic pipeline depth control
- Patent number 6,009,477
- Issue date Dec 28, 1999
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus system providing dynamic control of pipeline depth for a multi-...
- Patent number 5,948,088
- Issue date Sep 7, 1999
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting read, write, and invalidation o...
- Patent number 5,909,699
- Issue date Jun 1, 1999
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization mechanism for symmetric arbitration agents
- Patent number 5,901,297
- Issue date May 4, 1999
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system providing a universal architecture adaptive to a va...
- Patent number 5,896,513
- Issue date Apr 20, 1999
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signaling protocol conversion between a processor and a high-perfor...
- Patent number 5,845,107
- Issue date Dec 1, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maintaining cache coherency using a single...
- Patent number 5,832,534
- Issue date Nov 3, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache memory replacement line identification
- Patent number 5,809,524
- Issue date Sep 15, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating bus clock signals with a 1/N characteristi...
- Patent number 5,802,132
- Issue date Sep 1, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly pipelined bus architecture
- Patent number 5,796,977
- Issue date Aug 18, 1998
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for self-snooping a bus during a boundary tran...
- Patent number 5,797,026
- Issue date Aug 18, 1998
- Intel Corporation
- Michael W. Rhodehamel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically controlling bus access from a...
- Patent number 5,784,579
- Issue date Jul 21, 1998
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing split lock variables in a comput...
- Patent number 5,778,441
- Issue date Jul 7, 1998
- Intel Corporation
- Michael W. Rhodehamel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor subsystem for use with a universal computer architecture
- Patent number 5,764,934
- Issue date Jun 9, 1998
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus system providing dynamic control of pipeline depth for a multi-...
- Patent number 5,761,449
- Issue date Jun 2, 1998
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing synchronous data transmission be...
- Patent number 5,754,833
- Issue date May 19, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for maintaining multilevel cache hierarchy coherency in a...
- Patent number 5,715,428
- Issue date Feb 3, 1998
- Intel Corporation
- Wen-Hann Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transferring information between a process...
- Patent number 5,701,503
- Issue date Dec 23, 1997
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system that maintains system wide cache coherency during d...
- Patent number 5,682,516
- Issue date Oct 28, 1997
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing operations based upon the addre...
- Patent number 5,636,374
- Issue date Jun 3, 1997
- Intel Corporation
- Scott D. Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system and method for maintaining memory consistency in a...
- Patent number 5,623,628
- Issue date Apr 22, 1997
- Intel Corporation
- James M. Brayton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number 5,615,343
- Issue date Mar 25, 1997
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with distributed bus arbitration scheme for symmetr...
- Patent number 5,581,782
- Issue date Dec 3, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting read, write, and invalidation o...
- Patent number 5,572,702
- Issue date Nov 5, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically controlling the current maximu...
- Patent number 5,548,733
- Issue date Aug 20, 1996
- Intel Corporation
- Nitin Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
UTILIZATION BASED INSTALLATION ON A COMPUTING SYSTEM
- Publication number 20080154805
- Publication date Jun 26, 2008
- Nagasubramanian Gurumoorthy
- G06 - COMPUTING CALCULATING COUNTING

Michael Rhodehamel

Person

Patents Grantslast 30 patents

Utilization based installation on a computing system

Method and apparatus for performing deferred transactions

Apparatus for generating bus clock signals with a 1/N characteristi...

Auto-configuration support for multiple processor-ready pair or FRC...

Control register bus access through a standardized test access port

Bus agent providing dynamic pipeline depth control

Bus system providing dynamic control of pipeline depth for a multi-...

Method and apparatus for supporting read, write, and invalidation o...

Initialization mechanism for symmetric arbitration agents

Computer system providing a universal architecture adaptive to a va...

Signaling protocol conversion between a processor and a high-perfor...

Method and apparatus for maintaining cache coherency using a single...

Method and apparatus for cache memory replacement line identification

Apparatus for generating bus clock signals with a 1/N characteristi...

Highly pipelined bus architecture

Method and apparatus for self-snooping a bus during a boundary tran...

Method and apparatus for dynamically controlling bus access from a...

Method and apparatus for accessing split lock variables in a comput...

Processor subsystem for use with a universal computer architecture

Bus system providing dynamic control of pipeline depth for a multi-...

Method and apparatus for providing synchronous data transmission be...

Apparatus for maintaining multilevel cache hierarchy coherency in a...

Method and apparatus for transferring information between a process...

Computer system that maintains system wide cache coherency during d...

Method and apparatus for performing operations based upon the addre...

Computer system and method for maintaining memory consistency in a...

Method and apparatus for performing deferred transactions

Computer system with distributed bus arbitration scheme for symmetr...

Method and apparatus for supporting read, write, and invalidation o...

Method and apparatus for dynamically controlling the current maximu...

Patents Applicationslast 30 patents

UTILIZATION BASED INSTALLATION ON A COMPUTING SYSTEM