Michael Scheppler

Person

Grobenzell, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Architecture of function blocks and wirings in a structured ASIC an...
- Patent number 7,755,110
- Issue date Jul 13, 2010
- Infineon Technologies AG
- Jörg Gliese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit arrangement for supplying configuration data in FPGA devices
- Patent number 7,492,187
- Issue date Feb 17, 2009
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mask-programmable logic macro and method for programming a logic macro
- Patent number 7,439,765
- Issue date Oct 21, 2008
- Infineon Technologies AG
- Winfried Kamp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configurable logic component without a local configuration memory a...
- Patent number 7,348,795
- Issue date Mar 25, 2008
- Infineon Technologies AG
- Michael Scheppler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Look-up table
- Patent number 7,323,904
- Issue date Jan 29, 2008
- Infineon Technologies AG
- Francisco-Javier Veredas-Ramirez
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic circuit arrangement
- Patent number 7,199,618
- Issue date Apr 3, 2007
- Infineon Technologies AG
- Jörg Gliese
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Architecture of Function Blocks and Wirings in a Structured ASIC an...
- Publication number 20100308863
- Publication date Dec 9, 2010
- Jorg Gliese
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Mask-programmable logic macro and method for programming a logic macro
- Publication number 20060279329
- Publication date Dec 14, 2006
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit arrangement for supplying configuration data in FPGA devices
- Publication number 20060273823
- Publication date Dec 7, 2006
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Architecture of function blocks and wirings in a structured ASIC an...
- Publication number 20050212562
- Publication date Sep 29, 2005
- Jorg Gliese
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic component without a local configuration memory a...
- Publication number 20050184755
- Publication date Aug 25, 2005
- Michael Scheppler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Look-up table
- Publication number 20050174144
- Publication date Aug 11, 2005
- Infineon Technologies AG
- Francisco-Javier Veredas-Ramirez
- G11 - INFORMATION STORAGE
Information Patent Application
Logic circuit arrangement
- Publication number 20050134317
- Publication date Jun 23, 2005
- Infineon Technologies AG
- Jorg Gliese
- H03 - BASIC ELECTRONIC CIRCUITRY

Michael Scheppler

Person

Patents Grantslast 30 patents

Architecture of function blocks and wirings in a structured ASIC an...

Circuit arrangement for supplying configuration data in FPGA devices

Mask-programmable logic macro and method for programming a logic macro

Configurable logic component without a local configuration memory a...

Look-up table

Logic circuit arrangement

Patents Applicationslast 30 patents

Architecture of Function Blocks and Wirings in a Structured ASIC an...

Mask-programmable logic macro and method for programming a logic macro

Circuit arrangement for supplying configuration data in FPGA devices

Architecture of function blocks and wirings in a structured ASIC an...

Configurable logic component without a local configuration memory a...

Look-up table

Logic circuit arrangement