Michael V. DeBole

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compound instruction set architecture for a neural inference chip
- Patent number 11,263,011
- Issue date Mar 1, 2022
- International Business Machines Corporation
- Andrew S. Cassidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for the alignment and locking of removable ele...
- Patent number 11,171,450
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Camillo Sassano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Streaming programmable point mapper and compute hardware
- Patent number 11,144,553
- Issue date Oct 12, 2021
- International Business Machines Corporation
- David J. Berg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Drawer latching assembly
- Patent number 10,966,522
- Issue date Apr 6, 2021
- International Business Machines Corporation
- Camillo Sassano
- E05 - LOCKS KEYS WINDOW OR DOOR FITTINGS SAFES
Information Patent Grant
Memory-mapped interface to message-passing computing systems
- Patent number 10,838,860
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-mapped interface for message passing computing systems
- Patent number 10,452,540
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY-MAPPED NEURAL NETWORK ACCELERATOR FOR DEPLOYABLE INFERENCE S...
- Publication number 20220101108
- Publication date Mar 31, 2022
- International Business Machines Corporation
- Filipp Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D NEURAL INFERENCE PROCESSING UNIT ARCHITECTURES
- Publication number 20210125040
- Publication date Apr 29, 2021
- International Business Machines Corporation
- Andrew S. Cassidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAWER LATCHING ASSEMBLY
- Publication number 20210015258
- Publication date Jan 21, 2021
- International Business Machines Corporation
- Camillo Sassano
- A47 - FURNITURE DOMESTIC ARTICLES OR APPLIANCES COFFEE MILLS SPICE MILLS SUCT...
Information Patent Application
METHOD AND APPARATUS FOR THE ALIGNMENT AND LOCKING OF REMOVABLE ELE...
- Publication number 20210013676
- Publication date Jan 14, 2021
- International Business Machines Corporation
- Camillo Sassano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOUND INSTRUCTION SET ARCHITECTURE FOR A NEURAL INFERENCE CHIP
- Publication number 20200167158
- Publication date May 28, 2020
- International Business Machines Corporation
- Andrew S. Cassidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-MAPPED INTERFACE TO MESSAGE-PASSING COMPUTING SYSTEMS
- Publication number 20200004678
- Publication date Jan 2, 2020
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-MAPPED INTERFACE FOR MESSAGE PASSING COMPUTING SYSTEMS
- Publication number 20190121734
- Publication date Apr 25, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G11 - INFORMATION STORAGE
Information Patent Application
STREAMING PROGRAMMABLE POINT MAPPER AND COMPUTE HARDWARE
- Publication number 20170155698
- Publication date Jun 1, 2017
- International Business Machines Corporation
- David J. Berg
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Michael V. DeBole

Person

Patents Grantslast 30 patents

Compound instruction set architecture for a neural inference chip

Method and apparatus for the alignment and locking of removable ele...

Streaming programmable point mapper and compute hardware

Drawer latching assembly

Memory-mapped interface to message-passing computing systems

Memory-mapped interface for message passing computing systems

Patents Applicationslast 30 patents

MEMORY-MAPPED NEURAL NETWORK ACCELERATOR FOR DEPLOYABLE INFERENCE S...

3D NEURAL INFERENCE PROCESSING UNIT ARCHITECTURES

DRAWER LATCHING ASSEMBLY

METHOD AND APPARATUS FOR THE ALIGNMENT AND LOCKING OF REMOVABLE ELE...

COMPOUND INSTRUCTION SET ARCHITECTURE FOR A NEURAL INFERENCE CHIP

MEMORY-MAPPED INTERFACE TO MESSAGE-PASSING COMPUTING SYSTEMS

MEMORY-MAPPED INTERFACE FOR MESSAGE PASSING COMPUTING SYSTEMS

STREAMING PROGRAMMABLE POINT MAPPER AND COMPUTE HARDWARE