Michael W. Morrow

Person

Mossisville, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combining load or store instructions
- Patent number 11,593,117
- Issue date Feb 28, 2023
- QUALCOMM Incorporated
- Harsh Thakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing instructions to execution pipelines based on register-assoc...
- Patent number 9,858,077
- Issue date Jan 2, 2018
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache tag compression
- Patent number 9,514,061
- Issue date Dec 6, 2016
- QUALCOMM Incorporated
- Henry Arthur Pellerin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fusing immediate value, write-based instructions in instruction pro...
- Patent number 9,477,476
- Issue date Oct 25, 2016
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi level indirect predictor using confidence counter and program...
- Patent number 9,477,478
- Issue date Oct 25, 2016
- QUALCOMM Incorporated
- Kulin N. Kothari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Moveable locked lines in a multi-level cache
- Patent number 9,430,385
- Issue date Aug 30, 2016
- Micron Technology, Inc.
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Establishing a branch target instruction cache (BTIC) entry for sub...
- Patent number 9,317,293
- Issue date Apr 19, 2016
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fusing conditional write instructions having opposite conditions in...
- Patent number 9,195,466
- Issue date Nov 24, 2015
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eliminating redundant masking operations instruction processing cir...
- Patent number 9,146,741
- Issue date Sep 29, 2015
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to selectively power functional units
- Patent number 9,146,607
- Issue date Sep 29, 2015
- Marvell International Ltd.
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management unit with pre-filling capability
- Patent number 9,092,358
- Issue date Jul 28, 2015
- QUALCOMM Incorporated
- Bohuslav Rychlik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for adaptive thread scheduling on asymmetric...
- Patent number 9,043,795
- Issue date May 26, 2015
- QUALCOMM Incorporated
- Michael William Morrow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods and apparatus for low intrusion snoop invalidation
- Patent number 8,856,448
- Issue date Oct 7, 2014
- QUALCOMM Incorporated
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to selectively power functional units
- Patent number 8,732,490
- Issue date May 20, 2014
- Marvell International Ltd.
- Dennis M. O'Connor
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Moveable locked lines in a multi-level cache
- Patent number 8,533,395
- Issue date Sep 10, 2013
- Micron Technology, Inc.
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing counter saturation in a filter
- Patent number 8,521,962
- Issue date Aug 27, 2013
- QUALCOMM Incorporated
- Vimal K. Reddy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and a system for accelerating procedure return sequences
- Patent number 8,341,383
- Issue date Dec 25, 2012
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to selectively power functional units
- Patent number 8,112,643
- Issue date Feb 7, 2012
- Marvell International Ltd.
- Dennis M. O'Connor
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Apparatus and methods for low-complexity instruction prefetch system
- Patent number 8,060,701
- Issue date Nov 15, 2011
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer prediction mechanism
- Patent number 7,987,337
- Issue date Jul 26, 2011
- Marvell International Ltd.
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for setting cache policies in a processor
- Patent number 7,949,834
- Issue date May 24, 2011
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetch throttle
- Patent number 7,917,702
- Issue date Mar 29, 2011
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power semi-trace instruction/trace hybrid cache with logic for...
- Patent number 7,822,925
- Issue date Oct 26, 2010
- Marvell International Ltd.
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for reducing number of lookups in a branch target address ca...
- Patent number 7,640,422
- Issue date Dec 29, 2009
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching processor threads during long latencies
- Patent number 7,596,683
- Issue date Sep 29, 2009
- Intel Corporation
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low locality-of-reference support in a multi-level cache hierachy
- Patent number 7,581,065
- Issue date Aug 25, 2009
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient memory hierarchy management
- Patent number 7,552,283
- Issue date Jun 23, 2009
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to enable execution of a thread in a multi-thr...
- Patent number 7,472,390
- Issue date Dec 30, 2008
- Intel Corporation
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for recognizing a subroutine call
- Patent number 7,444,501
- Issue date Oct 28, 2008
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power semi-trace instruction/trace hybrid cache with logic for...
- Patent number 7,437,512
- Issue date Oct 14, 2008
- Marvell International Ltd.
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMBINING LOAD OR STORE INSTRUCTIONS
- Publication number 20200004550
- Publication date Jan 2, 2020
- QUALCOMM Incorporated
- Harsh THAKKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH MECHANISMS WITH NON-EQUAL MAGNITUDE STRIDE
- Publication number 20180173631
- Publication date Jun 21, 2018
- QUALCOMM Incorporated
- Thomas Andrew SARTORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE-ALLOCATION FOR A CACHE BASED ON EXECUTE PERMISSIONS
- Publication number 20170255569
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Thomas Andrew SARTORIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINING LOADS OR STORES IN COMPUTER PROCESSING
- Publication number 20170249144
- Publication date Aug 31, 2017
- QUALCOMM Incorporated
- Kevin JAGET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING PREFETCH INSTRUCTIONS BASED ON INSTRUCTION ENCODING
- Publication number 20170046158
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Luke YEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING MEMORY INSTRUCTION PUNTS IN A COMPUTER PROCESSOR USING A...
- Publication number 20170046167
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Luke Yen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION
- Publication number 20160350116
- Publication date Dec 1, 2016
- QUALCOMM Incorporated
- Vimal Kodandarama REDDY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CACHE TAG COMPRESSION
- Publication number 20160342530
- Publication date Nov 24, 2016
- QUALCOMM Incorporated
- Henry Arthur PELLERIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELIMINATING REDUNDANCY IN A BRANCH TARGET INSTRUCTION CACHE BY ESTA...
- Publication number 20160335089
- Publication date Nov 17, 2016
- QUALCOMM Incorporated
- Vimal Kodandarama REDDY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOVING INVALID LITERAL LOAD VALUES, AND RELATED CIRCUITS, METHODS...
- Publication number 20160291981
- Publication date Oct 6, 2016
- QUALCOMM Incorporated
- Behnam Robatmili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROPAGATING CONSTANT VALUES USING A COMPUTED CONSTANTS TABLE, AND R...
- Publication number 20160092232
- Publication date Mar 31, 2016
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING CONSTANT VALUE GENERATION USING A COMPUTED CONSTANTS T...
- Publication number 20160092219
- Publication date Mar 31, 2016
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABL...
- Publication number 20160077836
- Publication date Mar 17, 2016
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPEN...
- Publication number 20140281391
- Publication date Sep 18, 2014
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE OPTIMIZATION OF HARD-TO-PREDICT SHORT FORWARD BRANCHES
- Publication number 20140281439
- Publication date Sep 18, 2014
- QUALCOMM Incorporated
- Vimal K. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fusing Immediate Value, Write-Based Instructions in Instruction Pro...
- Publication number 20140149722
- Publication date May 29, 2014
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUB...
- Publication number 20140149726
- Publication date May 29, 2014
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTIO...
- Publication number 20140047221
- Publication date Feb 13, 2014
- QUALCOMM Incorporated
- Andrew S. Irwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MOVEABLE LOCKED LINES IN A MULTI-LEVEL CACHE
- Publication number 20140013056
- Publication date Jan 9, 2014
- Micron Technology, Inc.
- Dennis M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Qualifying Software Branch-Target Hints with Hardware-Based Predict...
- Publication number 20140006752
- Publication date Jan 2, 2014
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISSUING INSTRUCTIONS TO EXECUTION PIPELINES BASED ON REGISTER-ASSOC...
- Publication number 20130326197
- Publication date Dec 5, 2013
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN...
- Publication number 20130311754
- Publication date Nov 21, 2013
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi Level Indirect Predictor using Confidence Counter and Program...
- Publication number 20130311760
- Publication date Nov 21, 2013
- QUALCOMM Incorporated
- Kulin N. Kothari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Eliminating Redundant Masking Operations Instruction Processing Cir...
- Publication number 20130290683
- Publication date Oct 31, 2013
- QUALCOMM Incorporated
- Melinda J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Hardware Pipeline Configured for Single-Instruction Addre...
- Publication number 20130086359
- Publication date Apr 4, 2013
- QUALCOMM Incorporated
- Subrato K. De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Management Unit With Pre-Filling Capability
- Publication number 20120226888
- Publication date Sep 6, 2012
- QUALCOMM Incorporated
- Bohuslav Rychlik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indirect Branch Hint
- Publication number 20110320787
- Publication date Dec 29, 2011
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatuses, Systems, and Methods for Reducing Translation Lookasid...
- Publication number 20110145542
- Publication date Jun 16, 2011
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Counter Saturation In A Filter
- Publication number 20110055489
- Publication date Mar 3, 2011
- QUALCOMM Incorporated
- Vimal K. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APARATUS FOR LOW INTRUSION SNOOP INVALIDATION
- Publication number 20100211744
- Publication date Aug 19, 2010
- QUALCOMM Incorporated
- Michael W. Morrow
- G06 - COMPUTING CALCULATING COUNTING

Michael W. Morrow

Person

Patents Grantslast 30 patents

Combining load or store instructions

Issuing instructions to execution pipelines based on register-assoc...

Method and apparatus for cache tag compression

Fusing immediate value, write-based instructions in instruction pro...

Multi level indirect predictor using confidence counter and program...

Moveable locked lines in a multi-level cache

Establishing a branch target instruction cache (BTIC) entry for sub...

Fusing conditional write instructions having opposite conditions in...

Eliminating redundant masking operations instruction processing cir...

Methods and apparatus to selectively power functional units

Memory management unit with pre-filling capability

Apparatus and methods for adaptive thread scheduling on asymmetric...

Methods and apparatus for low intrusion snoop invalidation

Methods and apparatus to selectively power functional units

Moveable locked lines in a multi-level cache

Managing counter saturation in a filter

Method and a system for accelerating procedure return sequences

Methods and apparatus to selectively power functional units

Apparatus and methods for low-complexity instruction prefetch system

Translation lookaside buffer prediction mechanism

Method and apparatus for setting cache policies in a processor

Data prefetch throttle

Low power semi-trace instruction/trace hybrid cache with logic for...

System for reducing number of lookups in a branch target address ca...

Switching processor threads during long latencies

Low locality-of-reference support in a multi-level cache hierachy

Efficient memory hierarchy management

Method and apparatus to enable execution of a thread in a multi-thr...

Methods and apparatus for recognizing a subroutine call

Low power semi-trace instruction/trace hybrid cache with logic for...

Patents Applicationslast 30 patents

COMBINING LOAD OR STORE INSTRUCTIONS

PREFETCH MECHANISMS WITH NON-EQUAL MAGNITUDE STRIDE

WRITE-ALLOCATION FOR A CACHE BASED ON EXECUTE PERMISSIONS

COMBINING LOADS OR STORES IN COMPUTER PROCESSING

DETERMINING PREFETCH INSTRUCTIONS BASED ON INSTRUCTION ENCODING

PREDICTING MEMORY INSTRUCTION PUNTS IN A COMPUTER PROCESSOR USING A...

MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION

METHOD AND APPARATUS FOR CACHE TAG COMPRESSION

ELIMINATING REDUNDANCY IN A BRANCH TARGET INSTRUCTION CACHE BY ESTA...

REMOVING INVALID LITERAL LOAD VALUES, AND RELATED CIRCUITS, METHODS...

PROPAGATING CONSTANT VALUES USING A COMPUTED CONSTANTS TABLE, AND R...

ACCELERATING CONSTANT VALUE GENERATION USING A COMPUTED CONSTANTS T...

PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABL...

METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPEN...

HARDWARE OPTIMIZATION OF HARD-TO-PREDICT SHORT FORWARD BRANCHES

Fusing Immediate Value, Write-Based Instructions in Instruction Pro...

ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUB...

FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTIO...

MOVEABLE LOCKED LINES IN A MULTI-LEVEL CACHE

Qualifying Software Branch-Target Hints with Hardware-Based Predict...

ISSUING INSTRUCTIONS TO EXECUTION PIPELINES BASED ON REGISTER-ASSOC...

FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN...

Multi Level Indirect Predictor using Confidence Counter and Program...

Eliminating Redundant Masking Operations Instruction Processing Cir...

Processor Hardware Pipeline Configured for Single-Instruction Addre...

Memory Management Unit With Pre-Filling Capability

Indirect Branch Hint

Apparatuses, Systems, and Methods for Reducing Translation Lookasid...

Managing Counter Saturation In A Filter

METHODS AND APARATUS FOR LOW INTRUSION SNOOP INVALIDATION