Michael Wittke

Person

Pinneberg, DE

People

Patents Grantslast 30 patents

Information Patent Grant
High speed clock control
- Patent number 8,448,008
- Issue date May 21, 2013
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
On-chip logic to log failures during production testing and enable...
- Patent number 8,423,845
- Issue date Apr 16, 2013
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Testable integrated circuit and test data generation method
- Patent number 8,250,420
- Issue date Aug 21, 2012
- NXP B.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic logic built-in self-test stimuli generation
- Patent number 8,112,686
- Issue date Feb 7, 2012
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
On-chip logic to support compressed X-masking for BIST
- Patent number 8,103,925
- Issue date Jan 24, 2012
- Mentor Graphics Corporation
- Friedrich Hapke
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit arrangement and method of testing an application circuit pr...
- Patent number 7,870,453
- Issue date Jan 11, 2011
- NXP B.V.
- Michael Wittke
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
On-Chip Logic To Log Failures During Production Testing And Enable...
- Publication number 20110047425
- Publication date Feb 24, 2011
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Logic To Support Compressed X-Masking For BIST
- Publication number 20100299567
- Publication date Nov 25, 2010
- Friedrich Hapke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic Logic Built-In Self-Test Stimuli Generation
- Publication number 20100275075
- Publication date Oct 28, 2010
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIS...
- Publication number 20100253381
- Publication date Oct 7, 2010
- Friedrich Hapke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Speed Clock Control
- Publication number 20100251045
- Publication date Sep 30, 2010
- Mentor Graphics Corporation
- Friedrich HAPKE
- G01 - MEASURING TESTING
Information Patent Application
Cell-Aware Fault Model Creation And Pattern Generation
- Publication number 20100229061
- Publication date Sep 9, 2010
- Friedrich HAPKE
- G01 - MEASURING TESTING
Information Patent Application
TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD
- Publication number 20100117658
- Publication date May 13, 2010
- NXP, B.V.
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Application
Circuit Arrangement and Method of Testing an Application Circuit Pr...
- Publication number 20080195907
- Publication date Aug 14, 2008
- NXP B.V.
- Michael Wittke
- G01 - MEASURING TESTING
Information Patent Application
Method of testing an integrated circuit by simulation
- Publication number 20030128022
- Publication date Jul 10, 2003
- Laurent Souef
- G01 - MEASURING TESTING

Michael Wittke

Person

Patents Grantslast 30 patents

High speed clock control

On-chip logic to log failures during production testing and enable...

Testable integrated circuit and test data generation method

Deterministic logic built-in self-test stimuli generation

On-chip logic to support compressed X-masking for BIST

Circuit arrangement and method of testing an application circuit pr...

Patents Applicationslast 30 patents

On-Chip Logic To Log Failures During Production Testing And Enable...

On-Chip Logic To Support Compressed X-Masking For BIST

Deterministic Logic Built-In Self-Test Stimuli Generation

On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIS...

High Speed Clock Control

Cell-Aware Fault Model Creation And Pattern Generation

TESTABLE INTEGRATED CIRCUIT AND TEST DATA GENERATION METHOD

Circuit Arrangement and Method of Testing an Application Circuit Pr...

Method of testing an integrated circuit by simulation