Michele Petracca

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Chappaqua, NY, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for optimizing a verification test regression
- Patent number 11,868,241
- Issue date Jan 9, 2024
- Cadence Design Systems, Inc.
- Yael Kinderman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constrained metric optimization of a system on chip
- Patent number 10,607,039
- Issue date Mar 31, 2020
- Cadence Design Systems, Inc.
- Yael Kinderman
- G05 - CONTROLLING REGULATING
Information Patent Grant
Constrained metric verification analysis of a system on chip
- Patent number 10,423,741
- Issue date Sep 24, 2019
- Cadence Design Systems, Inc.
- Michele Petracca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Statistical sensitivity analyzer
- Patent number 10,409,939
- Issue date Sep 10, 2019
- Cadence Design Systems, Inc.
- Michele Petracca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Source code annotation for a system on chip
- Patent number 10,140,202
- Issue date Nov 27, 2018
- Cadence Design Systems, Inc.
- Michele Petracca
- G06 - COMPUTING CALCULATING COUNTING