Michele Quarantelli

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Noceto, IT

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Patents Grantslast 30 patents

Information Patent Grant
Layout for DUT arrays used in semiconductor wafer testing
- Patent number 7,489,151
- Issue date Feb 10, 2009
- PDF Solutions, Inc.
- Christopher Hess
- G01 - MEASURING TESTING
Information Patent Grant
Sensing circuit for memory cells
- Patent number 6,535,428
- Issue date Mar 18, 2003
- STMicroelectronics S.r.l.
- Marco Pasotti
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
- Publication number 20090140762
- Publication date Jun 4, 2009
- PDF Solutions, Inc.
- Christopher Hess
- G01 - MEASURING TESTING
Information Patent Application
Layout for DUT arrays used in semiconductor wafer testing
- Publication number 20070075718
- Publication date Apr 5, 2007
- PDF Solutions, Inc.
- Christopher Hess
- G01 - MEASURING TESTING
Information Patent Application
BIASING CIRCUIT FOR MULTI-LEVEL MEMORY CELLS
- Publication number 20020196664
- Publication date Dec 26, 2002
- Marco Pasotti
- G11 - INFORMATION STORAGE