Michiaki Muraoka

Person

Machida, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Designing of a logic circuit for testability
- Patent number 7,437,340
- Issue date Oct 14, 2008
- Semiconductor Technology Academic Research Center
- Hiroshi Date
- G01 - MEASURING TESTING
Information Patent Grant
Method for co-verifying hardware and software for a semiconductor d...
- Patent number 7,155,690
- Issue date Dec 26, 2006
- Seiko Epson Corporation
- Hiroyuki Yamashita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IP base LSI designing system and designing method
- Patent number 6,961,913
- Issue date Nov 1, 2005
- Matsushita Electric Industrial Co., Ltd.
- Kaoru Okazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Database for designing integrated circuit device, and method for de...
- Patent number 6,526,561
- Issue date Feb 25, 2003
- Matsushita Electric Industrial Co., Ltd.
- Toshiyuki Yokoyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for automating top-down design processing for the design of...
- Patent number 5,963,730
- Issue date Oct 5, 1999
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution circuit with clock branch circuits connected to...
- Patent number 5,896,055
- Issue date Apr 20, 1999
- Matsushita Electronic Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis method and logic synthesis apparatus
- Patent number 5,673,200
- Issue date Sep 30, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatically arranging circuit elements i...
- Patent number 5,657,243
- Issue date Aug 12, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for functional level data interface
- Patent number 5,623,417
- Issue date Apr 22, 1997
- Matsushita Electric Industrial Co., Ltd.
- Chie Iwasaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for classifying and evaluating logic circuit
- Patent number 5,490,083
- Issue date Feb 6, 1996
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IP-based LSI design system and design method
- Publication number 20060036974
- Publication date Feb 16, 2006
- Matsushita Electric Industrial Co., Ltd.
- Kaoru Okazaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware/software co-verification method
- Publication number 20050149897
- Publication date Jul 7, 2005
- Hiroyuki Yamashita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compacted test plan generation for integrated circuit testing, test...
- Publication number 20030188239
- Publication date Oct 2, 2003
- Toshinori Hosokawa
- G01 - MEASURING TESTING
Information Patent Application
Designing of logic circuit for testability
- Publication number 20030097347
- Publication date May 22, 2003
- Hiroshi Date
- G01 - MEASURING TESTING
Information Patent Application
DATABASE FOR DESIGNING INTEGRATED CIRCUIT DEVICE AND METHOD FOR DES...
- Publication number 20030014729
- Publication date Jan 16, 2003
- TOSHIYUKI YOKOYAMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Database for designing integrated circuit device, and method for de...
- Publication number 20020184602
- Publication date Dec 5, 2002
- Matsushita Electric Industrial Co., Ltd.
- Toshiyuki Yokoyama
- G06 - COMPUTING CALCULATING COUNTING

Michiaki Muraoka

Person

Patents Grantslast 30 patents

Designing of a logic circuit for testability

Method for co-verifying hardware and software for a semiconductor d...

IP base LSI designing system and designing method

Database for designing integrated circuit device, and method for de...

Method for automating top-down design processing for the design of...

Clock distribution circuit with clock branch circuits connected to...

Logic synthesis method and logic synthesis apparatus

Method and apparatus for automatically arranging circuit elements i...

Method and apparatus for functional level data interface

Method and apparatus for classifying and evaluating logic circuit

Patents Applicationslast 30 patents

IP-based LSI design system and design method

Hardware/software co-verification method

Compacted test plan generation for integrated circuit testing, test...

Designing of logic circuit for testability

DATABASE FOR DESIGNING INTEGRATED CIRCUIT DEVICE AND METHOD FOR DES...

Database for designing integrated circuit device, and method for de...