Michiel Jos Van Duuren

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Electric device with a layer of conductive material contacted by na...
- Patent number 9,231,201
- Issue date Jan 5, 2016
- NXP B.V.
- Robertus Theodorus Fransiscus Van Schaijk
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Shallow trench isolation in floating gate devices
- Patent number 7,763,512
- Issue date Jul 27, 2010
- NXP B.V.
- Robertus Theodorus Fransiscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with erase gate on isolation zones
- Patent number 7,709,879
- Issue date May 4, 2010
- NXP B.V.
- Robertus Theodorus Fransiscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device
- Patent number 7,429,513
- Issue date Sep 30, 2008
- NXP B.V.
- Michiel Jos Van Duuren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation in floating gate devices
- Patent number 7,419,875
- Issue date Sep 2, 2008
- NXP B.V.
- Robertus Theodorus Fransiscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned 2-bit “double poly CMP” flash memory cell
- Patent number 7,214,579
- Issue date May 8, 2007
- NXP B.V.
- Franciscus Petrus Widdershoven
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate memory cells with increased coupling radio
- Patent number 7,045,852
- Issue date May 16, 2006
- Koninklijke Philips Electronics N.V.
- Michiel Jos Van Duuren
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for manufacturing an electric device with a layer of conduct...
- Publication number 20090200536
- Publication date Aug 13, 2009
- Koninklijke Philips Electronics N.V.
- Robertus Theodorus Franciscus Van Schaijk
- G11 - INFORMATION STORAGE
Information Patent Application
Shallow Trench Isolation in Floating Gate Devices
- Publication number 20080303076
- Publication date Dec 11, 2008
- Robertus Theodorus Fransiscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory with Erase Gate on Isolation Zones
- Publication number 20080203463
- Publication date Aug 28, 2008
- Koninklijke Philips Electronics N.V.
- Robertus Theodorus Fransiscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory cell and method of fabrication
- Publication number 20060220093
- Publication date Oct 5, 2006
- Koninklijke Philips Electronics N.V.
- Robertus Theodorus Franciscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned 2-bit "double poly cmp" flash memory cell
- Publication number 20060163642
- Publication date Jul 27, 2006
- Koninklijke Philips Electronics N.V.
- Franciscus Petrus Widdershoven
- G11 - INFORMATION STORAGE
Information Patent Application
Denise array structure for non-volatile semiconductor memories
- Publication number 20060145192
- Publication date Jul 6, 2006
- Michiel Jos Van Duuren
- G11 - INFORMATION STORAGE
Information Patent Application
Shallow trench isolation in floating gate devices
- Publication number 20060118861
- Publication date Jun 8, 2006
- Koninklijke Philips Electronics N.V.
- Robertus Theodorus Franciscus Van Schaijk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Floating gate memory cells with increased coupling radio
- Publication number 20050218445
- Publication date Oct 6, 2005
- Koninklijke Philips Electronics N.V.
- Michiel Jos Van Duuren
- H01 - BASIC ELECTRIC ELEMENTS

Michiel Jos Van Duuren

Person

Patents Grantslast 30 patents

Electric device with a layer of conductive material contacted by na...

Shallow trench isolation in floating gate devices

Non-volatile memory with erase gate on isolation zones

Method of manufacturing a semiconductor device

Shallow trench isolation in floating gate devices

Self-aligned 2-bit “double poly CMP” flash memory cell

Floating gate memory cells with increased coupling radio

Patents Applicationslast 30 patents

Method for manufacturing an electric device with a layer of conduct...

Shallow Trench Isolation in Floating Gate Devices

Non-Volatile Memory with Erase Gate on Isolation Zones

Non-volatile memory cell and method of fabrication

Self-aligned 2-bit "double poly cmp" flash memory cell

Denise array structure for non-volatile semiconductor memories

Shallow trench isolation in floating gate devices

Floating gate memory cells with increased coupling radio