Mickey L. Fandrich

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for testing removable flash memory devices
- Patent number 7,624,316
- Issue date Nov 24, 2009
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronizing user commands to a microcontroller in a memory device
- Patent number 6,370,651
- Issue date Apr 9, 2002
- Intel Corporation
- Richard J. Durante
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for queuing and absorbing erase commands in a nonvolatile m...
- Patent number 5,956,742
- Issue date Sep 21, 1999
- Intel Corporation
- Mickey Lee Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling flash memory program and erase pulses
- Patent number 5,944,837
- Issue date Aug 31, 1999
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling flash memory program and erase pulses
- Patent number 5,907,700
- Issue date May 25, 1999
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry for propagating test mode signals associated with a memor...
- Patent number 5,850,509
- Issue date Dec 15, 1998
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Special test modes for a page buffer shared resource in a memory de...
- Patent number 5,835,927
- Issue date Nov 10, 1998
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for prioritizing erase and program commands in a nonvolatil...
- Patent number 5,809,541
- Issue date Sep 15, 1998
- Intel Corporation
- Mickey Lee Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for allocating and sharingpage buffers for a flas...
- Patent number 5,802,552
- Issue date Sep 1, 1998
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of prioritizing subsequently received program and erase comm...
- Patent number 5,802,343
- Issue date Sep 1, 1998
- Intel Corporation
- Mickey Lee Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a central control bus and a control access regis...
- Patent number 5,748,939
- Issue date May 5, 1998
- Intel Corporation
- Rodney R. Rozman
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible user interface circuit in a memory device
- Patent number 5,692,138
- Issue date Nov 25, 1997
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special test modes for a page buffer shared resource in a memory de...
- Patent number 5,623,620
- Issue date Apr 22, 1997
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for selectively locking write access to blocks in...
- Patent number 5,592,641
- Issue date Jan 7, 1997
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for reconfiguring a flash memory
- Patent number 5,574,850
- Issue date Nov 12, 1996
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for queuing snooping, prioritizing and suspend...
- Patent number 5,559,988
- Issue date Sep 24, 1996
- Intel Corporation
- Richard J. Durante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and method for selectively protecting the integrity of da...
- Patent number 5,546,561
- Issue date Aug 13, 1996
- Intel Corporation
- Virgil N. Kynett
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for preconditioning a nonvolatile memory array
- Patent number 5,537,357
- Issue date Jul 16, 1996
- Intel Corporation
- Amit Merchant
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of pipelining sequential writes in a flash memory
- Patent number 5,519,847
- Issue date May 21, 1996
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory with blocks and circuitry for selectively protec...
- Patent number 5,513,136
- Issue date Apr 30, 1996
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for programming and erasing a non-volatile sem...
- Patent number 5,513,333
- Issue date Apr 30, 1996
- Intel Corporation
- Virgil N. Kynett
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for execution of operations in a flash memory...
- Patent number 5,509,134
- Issue date Apr 16, 1996
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command interface between user commands and a memory device
- Patent number 5,463,757
- Issue date Oct 31, 1995
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for programming and erasing a non-volatile sem...
- Patent number 5,448,712
- Issue date Sep 5, 1995
- Intel Corporation
- Virgil N. Kynett
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture for reading information from a memory array
- Patent number 5,430,677
- Issue date Jul 4, 1995
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Override timing control circuitry and method for terminating progra...
- Patent number 5,414,829
- Issue date May 9, 1995
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing erase characteristics of a flash memory array
- Patent number 5,412,793
- Issue date May 2, 1995
- Intel Corporation
- Jerry Kreifels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary test scheme for an intelligent device
- Patent number 5,377,199
- Issue date Dec 27, 1994
- Intel Corporation
- Mickey L. Fandrich
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuitry for preconditioning shorted rows in a nonvolat...
- Patent number 5,377,147
- Issue date Dec 27, 1994
- Intel Corporation
- Amit Merchant
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for programming and erasing a non-volatile sem...
- Patent number 5,377,145
- Issue date Dec 27, 1994
- Intel Corporation
- Virgil N. Kynett
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Testing memory integrated circuits
- Publication number 20070145363
- Publication date Jun 28, 2007
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory management apparatus, systems, and methods
- Publication number 20060143371
- Publication date Jun 29, 2006
- John C. Rudelic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing reclamation for removable data devices
- Publication number 20060107014
- Publication date May 18, 2006
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING

Mickey L. Fandrich

Person

Patents Grantslast 30 patents

Apparatus and method for testing removable flash memory devices

Synchronizing user commands to a microcontroller in a memory device

Methods for queuing and absorbing erase commands in a nonvolatile m...

Controlling flash memory program and erase pulses

Controlling flash memory program and erase pulses

Circuitry for propagating test mode signals associated with a memor...

Special test modes for a page buffer shared resource in a memory de...

Methods for prioritizing erase and program commands in a nonvolatil...

System and method for allocating and sharingpage buffers for a flas...

Method of prioritizing subsequently received program and erase comm...

Memory device with a central control bus and a control access regis...

Flexible user interface circuit in a memory device

Special test modes for a page buffer shared resource in a memory de...

Method and device for selectively locking write access to blocks in...

Circuitry and method for reconfiguring a flash memory

Method and circuitry for queuing snooping, prioritizing and suspend...

Circuitry and method for selectively protecting the integrity of da...

Method for preconditioning a nonvolatile memory array

Method of pipelining sequential writes in a flash memory

Nonvolatile memory with blocks and circuitry for selectively protec...

Circuitry and method for programming and erasing a non-volatile sem...

Method and apparatus for execution of operations in a flash memory...

Command interface between user commands and a memory device

Circuitry and method for programming and erasing a non-volatile sem...

Architecture for reading information from a memory array

Override timing control circuitry and method for terminating progra...

Method for testing erase characteristics of a flash memory array

Boundary test scheme for an intelligent device

Method and circuitry for preconditioning shorted rows in a nonvolat...

Circuitry and method for programming and erasing a non-volatile sem...

Patents Applicationslast 30 patents

Testing memory integrated circuits

Integrated memory management apparatus, systems, and methods

Managing reclamation for removable data devices