Midori Takano

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Tokyo, JP

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for the optimization of a tree depth for clock...
- Patent number 6,230,300
- Issue date May 8, 2001
- Kabushiki Kaisha Toshiba
- Midori Takano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout method of wiring pattern for semiconductor integrated circuit
- Patent number 5,801,960
- Issue date Sep 1, 1998
- Kabushiki Kaisha Toshiba
- Midori Takano
- G06 - COMPUTING CALCULATING COUNTING