Miguel Comparan

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor with hybrid pipeline capable of operating in out-of-order...
- Patent number 10,831,504
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with hybrid pipeline capable of operating in out-of-order...
- Patent number 10,114,652
- Issue date Oct 30, 2018
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with hybrid pipeline capable of operating in out-of-order...
- Patent number 9,354,884
- Issue date May 31, 2016
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocating cache for use as a dedicated local storage
- Patent number 9,092,347
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocating cache for use as a dedicated local storage
- Patent number 9,053,037
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency variable transfer network communicating variable writte...
- Patent number 9,021,237
- Issue date Apr 28, 2015
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transferring architected state between cores
- Patent number 8,954,973
- Issue date Feb 10, 2015
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transferring architected state between cores
- Patent number 8,949,836
- Issue date Feb 3, 2015
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core processor with internal voting-based built in self test...
- Patent number 8,856,602
- Issue date Oct 7, 2014
- International Business Machines Corporation
- Jeffrey D. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Near neighbor data cache sharing
- Patent number 8,719,508
- Issue date May 6, 2014
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Near neighbor data cache sharing
- Patent number 8,719,507
- Issue date May 6, 2014
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard memory array failure recovery utilizing locking structure
- Patent number 8,560,897
- Issue date Oct 15, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic data type aligned cache optimized for misaligned packed str...
- Patent number 8,493,398
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network on chip
- Patent number 8,392,664
- Issue date Mar 5, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anisotropic texture filtering with texture data prefetching
- Patent number 8,310,497
- Issue date Nov 13, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anisotropic texture filtering with texture data prefetching
- Patent number 8,217,953
- Issue date Jul 10, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for executing instructions
- Patent number 8,082,420
- Issue date Dec 20, 2011
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network on chip that maintains cache coherency with invalidate comm...
- Patent number 8,010,750
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network on chip that maintains cache coherency with invalidate comm...
- Patent number 7,917,703
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing unit incorporating L1 cache bypass
- Patent number 7,890,699
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...
- Publication number 20190034208
- Publication date Jan 31, 2019
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...
- Publication number 20160224351
- Publication date Aug 4, 2016
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...
- Publication number 20140281402
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEAR NEIGHBOR DATA CACHE SHARING
- Publication number 20130173861
- Publication date Jul 4, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEAR NEIGHBOR DATA CACHE SHARING
- Publication number 20130173860
- Publication date Jul 4, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE
- Publication number 20130173967
- Publication date Jul 4, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE PROCESSOR WITH INTERNAL VOTING-BASED BUILT IN SELF TEST...
- Publication number 20130159799
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Jeffrey D. Brown
- G01 - MEASURING TESTING
Information Patent Application
LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM...
- Publication number 20130159669
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSFERRING ARCHITECTED STATE BETWEEN CORES
- Publication number 20130097411
- Publication date Apr 18, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE
- Publication number 20130086329
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSFERRING ARCHITECTED STATE BETWEEN CORES
- Publication number 20120254877
- Publication date Oct 4, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE
- Publication number 20120254548
- Publication date Oct 4, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANISOTROPIC TEXTURE FILTERING WITH TEXTURE DATA PREFETCHING
- Publication number 20120169755
- Publication date Jul 5, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE
- Publication number 20120144253
- Publication date Jun 7, 2012
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Anisotropic Texture Filtering with Texture Data Prefetching
- Publication number 20090315908
- Publication date Dec 24, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network On Chip
- Publication number 20090282197
- Publication date Nov 12, 2009
- International Business Machines Corporation
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network On Chip
- Publication number 20090245257
- Publication date Oct 1, 2009
- International Business Machines Corporation
- Miguel Comparan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network On Chip that Maintains Cache Coherency with Invalidate Comm...
- Publication number 20090187716
- Publication date Jul 23, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing Unit Incorporating L1 Cache Bypass
- Publication number 20090182944
- Publication date Jul 16, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Data Type Aligned Cache Optimized for Misaligned Packed Str...
- Publication number 20090179902
- Publication date Jul 16, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network on Chip That Maintains Cache Coherency With Invalidate Comm...
- Publication number 20090157976
- Publication date Jun 18, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Executing Instructions
- Publication number 20090113181
- Publication date Apr 30, 2009
- Miguel Comparan
- G06 - COMPUTING CALCULATING COUNTING

Miguel Comparan

Person

Patents Grantslast 30 patents

Processor with hybrid pipeline capable of operating in out-of-order...

Processor with hybrid pipeline capable of operating in out-of-order...

Processor with hybrid pipeline capable of operating in out-of-order...

Allocating cache for use as a dedicated local storage

Allocating cache for use as a dedicated local storage

Low latency variable transfer network communicating variable writte...

Transferring architected state between cores

Transferring architected state between cores

Multi-core processor with internal voting-based built in self test...

Near neighbor data cache sharing

Near neighbor data cache sharing

Hard memory array failure recovery utilizing locking structure

Dynamic data type aligned cache optimized for misaligned packed str...

Network on chip

Anisotropic texture filtering with texture data prefetching

Anisotropic texture filtering with texture data prefetching

Method and apparatus for executing instructions

Network on chip that maintains cache coherency with invalidate comm...

Network on chip that maintains cache coherency with invalidate comm...

Processing unit incorporating L1 cache bypass

Patents Applicationslast 30 patents

PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...

PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...

PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER...

NEAR NEIGHBOR DATA CACHE SHARING

NEAR NEIGHBOR DATA CACHE SHARING

HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE

MULTI-CORE PROCESSOR WITH INTERNAL VOTING-BASED BUILT IN SELF TEST...

LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM...

TRANSFERRING ARCHITECTED STATE BETWEEN CORES

ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE

TRANSFERRING ARCHITECTED STATE BETWEEN CORES

ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE

ANISOTROPIC TEXTURE FILTERING WITH TEXTURE DATA PREFETCHING

HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE

Anisotropic Texture Filtering with Texture Data Prefetching

Network On Chip

Network On Chip

Network On Chip that Maintains Cache Coherency with Invalidate Comm...

Processing Unit Incorporating L1 Cache Bypass

Dynamic Data Type Aligned Cache Optimized for Misaligned Packed Str...

Network on Chip That Maintains Cache Coherency With Invalidate Comm...

Method and Apparatus for Executing Instructions