Mihir K. Roy

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
High density interconnect device and method
- Patent number 12,094,831
- Issue date Sep 17, 2024
- Tahoe Research, LTD.
- Mihir K Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic bridge device and method
- Patent number 12,002,762
- Issue date Jun 4, 2024
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density interconnect device and method
- Patent number 11,664,320
- Issue date May 30, 2023
- Tahoe Research, LTD.
- Mihir K Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Helical plated through-hole package inductor
- Patent number 11,608,564
- Issue date Mar 21, 2023
- Intel Corporation
- William J. Lambert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a package substrate
- Patent number 11,443,970
- Issue date Sep 13, 2022
- Intel Corporation
- Manohar S. Konchady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density interconnect device and method
- Patent number 11,158,578
- Issue date Oct 26, 2021
- Intel Corporation
- Mihir K Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an inductor
- Patent number 10,998,120
- Issue date May 4, 2021
- Intel Corporation
- William J. Lambert
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Package power delivery using plane and shaped vias
- Patent number 10,971,416
- Issue date Apr 6, 2021
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate conductor structure and method
- Patent number 10,734,282
- Issue date Aug 4, 2020
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic bridge device and method
- Patent number 10,672,713
- Issue date Jun 2, 2020
- Intel Corporation
- Mihir K. Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Solder resist layers for coreless packages and methods of fabrication
- Patent number 10,629,469
- Issue date Apr 21, 2020
- Intel Corporation
- Manohar S. Konchady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density interconnect device and method
- Patent number 10,446,499
- Issue date Oct 15, 2019
- Intel Corporation
- Mihir K Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package power delivery using plane and shaped vias
- Patent number 10,410,939
- Issue date Sep 10, 2019
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inductor formed in substrate
- Patent number 10,312,007
- Issue date Jun 4, 2019
- Intel Corporation
- Mihir K Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Helical plated through-hole package inductor
- Patent number 10,163,557
- Issue date Dec 25, 2018
- Intel Corporation
- William J. Lambert
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Substrate conductor structure and method
- Patent number 10,121,701
- Issue date Nov 6, 2018
- Intel Corporation
- Harold Ryan Chase
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High density organic bridge device and method
- Patent number 10,103,105
- Issue date Oct 16, 2018
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct chip attach using embedded traces
- Patent number 10,085,341
- Issue date Sep 25, 2018
- Intel Corporation
- Mihir K Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electrical interconnect formed through buildup process
- Patent number 10,028,394
- Issue date Jul 17, 2018
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device and method of manufacturing same
- Patent number 9,999,129
- Issue date Jun 12, 2018
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical interconnect formed through buildup process
- Patent number 9,955,589
- Issue date Apr 24, 2018
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with bi-layered dielectric structure
- Patent number 9,917,044
- Issue date Mar 13, 2018
- Intel Corporation
- Zheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid pitch package with ultra high density interconnect capability
- Patent number 9,899,311
- Issue date Feb 20, 2018
- Intel Corporation
- Mathew J. Manusharow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a semiconductor device substrate
- Patent number 9,820,390
- Issue date Nov 14, 2017
- Intel Corporation
- Mihir K. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic package and method of connecting a first die to a second...
- Patent number 9,741,686
- Issue date Aug 22, 2017
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced PTH pad for enabling core routing and substrate layer count...
- Patent number 9,711,441
- Issue date Jul 18, 2017
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual side solder resist layers for coreless packages and packages w...
- Patent number 9,704,735
- Issue date Jul 11, 2017
- Intel Corporation
- Manohar S. Konchady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid pitch package with ultra high density interconnect capability
- Patent number 9,633,938
- Issue date Apr 25, 2017
- Intel Corporation
- Mathew J. Manusharow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a circuit board
- Patent number 9,622,350
- Issue date Apr 11, 2017
- Intel Corporation
- Mihir K. Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Landside stiffening capacitors to enable ultrathin and other low-Z...
- Patent number 9,552,977
- Issue date Jan 24, 2017
- Intel Corporation
- Mihir K Roy
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH DENSITY INTERCONNECT DEVICE AND METHOD
- Publication number 20240421098
- Publication date Dec 19, 2024
- Tahoe Research, Ltd.
- Mihir K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
- Publication number 20240321762
- Publication date Sep 26, 2024
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY INTERCONNECT DEVICE AND METHOD
- Publication number 20230253337
- Publication date Aug 10, 2023
- Tahoe Research, Ltd.
- Mihir K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY INTERCONNECT DEVICE AND METHOD
- Publication number 20220028790
- Publication date Jan 27, 2022
- Intel Corporation
- MIHIR K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR
- Publication number 20210304952
- Publication date Sep 30, 2021
- Intel Corporation
- William J. Lambert
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
- Publication number 20200294924
- Publication date Sep 17, 2020
- Intel Corporation
- Mihir K. Roy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND METHODS OF FABRICATION
- Publication number 20200194300
- Publication date Jun 18, 2020
- Intel Corporation
- Manohar S. KONCHADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY INTERCONNECT DEVICE AND METHOD
- Publication number 20200111745
- Publication date Apr 9, 2020
- Intel Corporation
- MIHIR K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS
- Publication number 20190355636
- Publication date Nov 21, 2019
- Intel Corporation
- Krishna BHARATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR
- Publication number 20190051447
- Publication date Feb 14, 2019
- Intel Corporation
- William J. Lambert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
- Publication number 20190027405
- Publication date Jan 24, 2019
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
- Publication number 20190019755
- Publication date Jan 17, 2019
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS
- Publication number 20180331003
- Publication date Nov 15, 2018
- Intel Corporation
- Krishna BHARATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-COOLED LASER INTEGRATED DEVICE AND SUBSTRATE ARCHITECTURE
- Publication number 20180329240
- Publication date Nov 15, 2018
- Intel Corporation
- Vivek RAGHUNATHAN
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
VERTICALLY EMBEDDED PASSIVE COMPONENTS
- Publication number 20180332708
- Publication date Nov 15, 2018
- Intel Corporation
- William J. LAMBERT
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELECTRICAL INTERCONNECT FORMED THROUGH BUILDUP PROCESS
- Publication number 20180213655
- Publication date Jul 26, 2018
- Intel Corporation
- MIHIR K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SIDE SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND PACKAGES W...
- Publication number 20170250150
- Publication date Aug 31, 2017
- Intel Corporation
- Manohar S. KONCHADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIRECT CHIP ATTACH USING EMBEDDED TRACES
- Publication number 20170188460
- Publication date Jun 29, 2017
- Intel Corporation
- MIHIR K. ROY
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR
- Publication number 20170178786
- Publication date Jun 22, 2017
- William J. Lambert
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
HIGH DENSITY INTERCONNECT DEVICE AND METHOD
- Publication number 20170162509
- Publication date Jun 8, 2017
- Intel Corporation
- MIHIR K. ROY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
- Publication number 20170125349
- Publication date May 4, 2017
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH BI-LAYERED DIELECTRIC STRUCTURE
- Publication number 20170103941
- Publication date Apr 13, 2017
- Intel Corporation
- Zheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PITCH PACKAGE WITH ULTRA HIGH DENSITY INTERCONNECT CAPABILITY
- Publication number 20170092575
- Publication date Mar 30, 2017
- Intel Corporation
- Mathew J. MANUSHAROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PITCH PACKAGE WITH ULTRA HIGH DENSITY INTERCONNECT CAPABILITY
- Publication number 20170092573
- Publication date Mar 30, 2017
- Intel Corporation
- Mathew J. MANUSHAROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WEAVED ELECTRICAL COMPONENTS IN A SUBSTRATE PACKAGE CORE
- Publication number 20170027062
- Publication date Jan 26, 2017
- Intel Corporation
- MIHIR K. ROY
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
- Publication number 20160336223
- Publication date Nov 17, 2016
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC PACKAGE AND METHOD OF CONNECTING A FIRST DIE TO A SECOND...
- Publication number 20160204067
- Publication date Jul 14, 2016
- Intel Corporation
- Harold Ryan Chase
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT...
- Publication number 20160155694
- Publication date Jun 2, 2016
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD
- Publication number 20160133552
- Publication date May 12, 2016
- Intel Corporation
- Mihir K. Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SIDE SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND PACKAGES W...
- Publication number 20160056102
- Publication date Feb 25, 2016
- Manohar S. Konchady
- H01 - BASIC ELECTRIC ELEMENTS

Mihir K. Roy

Person

Patents Grantslast 30 patents

High density interconnect device and method

High density organic bridge device and method

High density interconnect device and method

Helical plated through-hole package inductor

Methods of forming a package substrate

High density interconnect device and method

Method of making an inductor

Package power delivery using plane and shaped vias

Substrate conductor structure and method

High density organic bridge device and method

Solder resist layers for coreless packages and methods of fabrication

High density interconnect device and method

Package power delivery using plane and shaped vias

Inductor formed in substrate

Helical plated through-hole package inductor

Substrate conductor structure and method

High density organic bridge device and method

Direct chip attach using embedded traces

Electrical interconnect formed through buildup process

Microelectronic device and method of manufacturing same

Electrical interconnect formed through buildup process

Package with bi-layered dielectric structure

Hybrid pitch package with ultra high density interconnect capability

Process for forming a semiconductor device substrate

Electronic package and method of connecting a first die to a second...

Reduced PTH pad for enabling core routing and substrate layer count...

Dual side solder resist layers for coreless packages and packages w...

Hybrid pitch package with ultra high density interconnect capability

Method of forming a circuit board

Landside stiffening capacitors to enable ultrathin and other low-Z...

Patents Applicationslast 30 patents

HIGH DENSITY INTERCONNECT DEVICE AND METHOD

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

HIGH DENSITY INTERCONNECT DEVICE AND METHOD

HIGH DENSITY INTERCONNECT DEVICE AND METHOD

HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND METHODS OF FABRICATION

HIGH DENSITY INTERCONNECT DEVICE AND METHOD

PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS

HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR

SUBSTRATE CONDUCTOR STRUCTURE AND METHOD

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS

SELF-COOLED LASER INTEGRATED DEVICE AND SUBSTRATE ARCHITECTURE

VERTICALLY EMBEDDED PASSIVE COMPONENTS

ELECTRICAL INTERCONNECT FORMED THROUGH BUILDUP PROCESS

DUAL SIDE SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND PACKAGES W...

DIRECT CHIP ATTACH USING EMBEDDED TRACES

HELICAL PLATED THROUGH-HOLE PACKAGE INDUCTOR

HIGH DENSITY INTERCONNECT DEVICE AND METHOD

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

PACKAGE WITH BI-LAYERED DIELECTRIC STRUCTURE

HYBRID PITCH PACKAGE WITH ULTRA HIGH DENSITY INTERCONNECT CAPABILITY

HYBRID PITCH PACKAGE WITH ULTRA HIGH DENSITY INTERCONNECT CAPABILITY

WEAVED ELECTRICAL COMPONENTS IN A SUBSTRATE PACKAGE CORE

SUBSTRATE CONDUCTOR STRUCTURE AND METHOD

ELECTRONIC PACKAGE AND METHOD OF CONNECTING A FIRST DIE TO A SECOND...

REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT...

HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD

DUAL SIDE SOLDER RESIST LAYERS FOR CORELESS PACKAGES AND PACKAGES W...