Mike Chih-Kang Liang

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multimedia redirection
- Patent number 8,793,331
- Issue date Jul 29, 2014
- Wyse Technology L.L.C.
- Daniel Ernesto Barreto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for building system images and split booting
- Patent number 8,452,952
- Issue date May 28, 2013
- Wyse Technology Inc.
- Mike Chih-Kang Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-chip integrated circuit routing to I/O devices
- Patent number 6,674,166
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Ramoji Karumuri Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Six-to-one signal/power ratio bump and trace pattern for flip chip...
- Patent number 6,591,410
- Issue date Jul 8, 2003
- LSI Logic Corporation
- Anwar Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip chip trace library generator
- Patent number 6,526,540
- Issue date Feb 25, 2003
- LSI Logic Corporation
- Eric Fong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design incorporating a power mesh
- Patent number 6,480,989
- Issue date Nov 12, 2002
- LSI Logic Corporation
- Chun Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I/O device layout during integrated circuit design
- Patent number 6,457,157
- Issue date Sep 24, 2002
- LSI Logic Corporation
- Virinder Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hexagonal arrangements of bump pads in flip-chip integrated circuits
- Patent number 6,323,559
- Issue date Nov 27, 2001
- LSI Logic Corporation
- Chun Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for netlist filtering and cell placement
- Patent number 6,243,849
- Issue date Jun 5, 2001
- LSI Logic Corporation
- Virinder Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-chip integrated circuit routing to I/O devices
- Patent number 6,225,143
- Issue date May 1, 2001
- LSI Logic Corporation
- Ramoji Karumuri Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die metal layout for flip chip packaging
- Patent number 6,118,180
- Issue date Sep 12, 2000
- LSI Logic Corporation
- Mike C. Loo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for I/O device layout during integrated circuit design
- Patent number 6,057,169
- Issue date May 2, 2000
- LSI Logic Corporation
- Virinder Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip chip bump distribution on die
- Patent number 5,952,726
- Issue date Sep 14, 1999
- LSI Logic Corporation
- Mike Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for distributing connection pads on a semiconductor die
- Patent number 5,885,855
- Issue date Mar 23, 1999
- LSI Logic Corporation
- Mike Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory having direct strap connection to power supply
- Patent number 5,808,900
- Issue date Sep 15, 1998
- LSI Logic Corporation
- Myron Buer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT INCORPORATING A POWER MESH
- Publication number 20010049813
- Publication date Dec 6, 2001
- CHUN CHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip-chip integrated circuit routing to I/O devices
- Publication number 20010020746
- Publication date Sep 13, 2001
- Ramoji Karumuri Rao
- H01 - BASIC ELECTRIC ELEMENTS

Mike Chih-Kang Liang

Person

Patents Grantslast 30 patents

Multimedia redirection

Methods and apparatus for building system images and split booting

Flip-chip integrated circuit routing to I/O devices

Six-to-one signal/power ratio bump and trace pattern for flip chip...

Flip chip trace library generator

Integrated circuit design incorporating a power mesh

I/O device layout during integrated circuit design

Hexagonal arrangements of bump pads in flip-chip integrated circuits

Method and apparatus for netlist filtering and cell placement

Flip-chip integrated circuit routing to I/O devices

Semiconductor die metal layout for flip chip packaging

Method for I/O device layout during integrated circuit design

Flip chip bump distribution on die

Method for distributing connection pads on a semiconductor die

Memory having direct strap connection to power supply

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT INCORPORATING A POWER MESH

Flip-chip integrated circuit routing to I/O devices