Miki Yanagawa

Person

Kawasaki, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device to select and output data to a data bus
- Patent number 8,572,424
- Issue date Oct 29, 2013
- Fujitsu Semiconductor Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Terminating resistance adjusting method, semiconductor integrated c...
- Patent number 7,639,038
- Issue date Dec 29, 2009
- Fujitsu Microelectronics Limited
- Yutaka Nemoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronization circuit for transferring data using a bus of a diff...
- Patent number 7,243,252
- Issue date Jul 10, 2007
- Fujitsu Limited
- Miki Yanagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Associative memory having a search bus driving circuit for supplyin...
- Patent number 6,885,571
- Issue date Apr 26, 2005
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Contents addressable memory with accelerated entry data shunting
- Patent number 6,567,286
- Issue date May 20, 2003
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory device with advanced precharge timing
- Patent number 6,560,133
- Issue date May 6, 2003
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory devices determining entry data priority...
- Patent number 6,542,392
- Issue date Apr 1, 2003
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory device with reduced power consumption
- Patent number 6,535,410
- Issue date Mar 18, 2003
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device using complementary clock and signal input sta...
- Patent number 6,509,763
- Issue date Jan 21, 2003
- Fujitsu Limited
- Masao Taguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
LSI device capable of adjusting the output impedance to match the c...
- Patent number 6,486,698
- Issue date Nov 26, 2002
- Fujitsu Limited
- Miki Yanagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory system and memory controller with reliable data latch operation
- Patent number 6,466,491
- Issue date Oct 15, 2002
- Fujitsu Limited
- Miki Yanagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device using complementary clock and signal input sta...
- Patent number 6,424,199
- Issue date Jul 23, 2002
- Fujitsu Limited
- Masao Taguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device using complementary clock and signal input sta...
- Patent number 6,225,841
- Issue date May 1, 2001
- Fujitsu Limited
- Masao Taguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device using complementary clock and signal input sta...
- Patent number 6,104,225
- Issue date Aug 15, 2000
- Fujitsu Limited
- Masao Taguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device reducing voltage consumption in voltage-detect...
- Patent number 5,994,888
- Issue date Nov 30, 1999
- Fujitsu Limited
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having voltage generation circuit
- Patent number 5,929,694
- Issue date Jul 27, 1999
- Fujitsu Limited
- Miki Yanagawa
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor device
- Publication number 20070240009
- Publication date Oct 11, 2007
- FUJITSU LIMITED
- Miki Yanagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Terminating resistance adjusting method, semiconductor integrated c...
- Publication number 20070216441
- Publication date Sep 20, 2007
- FUJITSU LIMITED
- Yutaka Nemoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Associative memory
- Publication number 20040008533
- Publication date Jan 15, 2004
- FUJITSU LIMITED
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device
- Publication number 20030197201
- Publication date Oct 23, 2003
- FUJITSU LIMITED
- Miki Yanagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LSI device capable of adjusting the output impedance to match the c...
- Publication number 20020196049
- Publication date Dec 26, 2002
- FUJITSU LIMITED
- Miki Yanagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Content addressable memory device with reduce power consumption
- Publication number 20020181264
- Publication date Dec 5, 2002
- FUJITSU LIMITED
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Contents addressable memory with accelerated entry data shunting
- Publication number 20020181263
- Publication date Dec 5, 2002
- FUJITSU LIMITED
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory device with advanced precharge timing
- Publication number 20020176270
- Publication date Nov 28, 2002
- FUJITSU LIMITED
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device using complementary clock and signal input sta...
- Publication number 20020153933
- Publication date Oct 24, 2002
- FUJITSU LIMITED
- Masao Taguchi
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory devices determining entry data priority...
- Publication number 20020145899
- Publication date Oct 10, 2002
- FUJITSU LIMITED
- Miki Yanagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device using complementary clock and signal input sta...
- Publication number 20020014903
- Publication date Feb 7, 2002
- FUJITSU LIMITED
- Masao Taquchi
- G11 - INFORMATION STORAGE
Information Patent Application
Memory system and memory controller with reliable data latch operation
- Publication number 20010046163
- Publication date Nov 29, 2001
- FUJITSU LIMITED
- Miki Yanagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LSI device
- Publication number 20010015882
- Publication date Aug 23, 2001
- FUJITSU LIMITED
- Miki Yanagawa
- H03 - BASIC ELECTRONIC CIRCUITRY

Miki Yanagawa

Person

Patents Grantslast 30 patents

Semiconductor device to select and output data to a data bus

Terminating resistance adjusting method, semiconductor integrated c...

Synchronization circuit for transferring data using a bus of a diff...

Associative memory having a search bus driving circuit for supplyin...

Contents addressable memory with accelerated entry data shunting

Content addressable memory device with advanced precharge timing

Content addressable memory devices determining entry data priority...

Content addressable memory device with reduced power consumption

Semiconductor device using complementary clock and signal input sta...

LSI device capable of adjusting the output impedance to match the c...

Memory system and memory controller with reliable data latch operation

Semiconductor device using complementary clock and signal input sta...

Semiconductor device using complementary clock and signal input sta...

Semiconductor device using complementary clock and signal input sta...

Semiconductor device reducing voltage consumption in voltage-detect...

Semiconductor device having voltage generation circuit

Patents Applicationslast 30 patents

Semiconductor device

Terminating resistance adjusting method, semiconductor integrated c...

Associative memory

Semiconductor device

LSI device capable of adjusting the output impedance to match the c...

Content addressable memory device with reduce power consumption

Contents addressable memory with accelerated entry data shunting

Content addressable memory device with advanced precharge timing

Semiconductor device using complementary clock and signal input sta...

Content addressable memory devices determining entry data priority...

Semiconductor device using complementary clock and signal input sta...

Memory system and memory controller with reliable data latch operation

LSI device