Milind P. Padhye

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Management of power domains in an integrated circuit
- Patent number 8,020,017
- Issue date Sep 13, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Techniques for operating a processor subsystem to service masked in...
- Patent number 7,779,284
- Issue date Aug 17, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Bhoodev Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speedpath repair in an integrated circuit
- Patent number 7,612,577
- Issue date Nov 3, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Mahbub M. Rashed
- G11 - INFORMATION STORAGE
Information Patent Grant
State retention within a data processing system
- Patent number 7,365,596
- Issue date Apr 29, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of data retention latches in circuit devices
- Patent number 7,346,820
- Issue date Mar 18, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- G01 - MEASURING TESTING
Information Patent Grant
State retention within a data processing system
- Patent number 7,183,825
- Issue date Feb 27, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip-flop circuit having low power data retention
- Patent number 7,138,842
- Issue date Nov 21, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop circuit having low power data retention
- Patent number 7,123,068
- Issue date Oct 17, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Andrew P. Hoover
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MANAGEMENT OF POWER DOMAINS IN AN INTEGRATED CIRCUIT
- Publication number 20100042858
- Publication date Feb 18, 2010
- Milind P. Padhye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPEEDPATH REPAIR IN AN INTEGRATED CIRCUIT
- Publication number 20090031163
- Publication date Jan 29, 2009
- Mahbub M. Rashed
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR OPERATING A PROCESSOR SUBSYSTEM
- Publication number 20080209233
- Publication date Aug 28, 2008
- BHOODEV KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing of data retention latches in circuit devices
- Publication number 20070226561
- Publication date Sep 27, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Milind P. Padhye
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP CIRCUIT HAVING LOW POWER DATA RETENTION
- Publication number 20060220717
- Publication date Oct 5, 2006
- Milind P. Padhye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flip-flop circuit having low power data retention
- Publication number 20060220700
- Publication date Oct 5, 2006
- Andrew P. Hoover
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
State retention within a data processing system
- Publication number 20050218952
- Publication date Oct 6, 2005
- Milind P. Padhye
- G11 - INFORMATION STORAGE
Information Patent Application
State retention within a data processing system
- Publication number 20050218943
- Publication date Oct 6, 2005
- Milind P. Padhye
- G06 - COMPUTING CALCULATING COUNTING

Milind P. Padhye

Person

Patents Grantslast 30 patents

Management of power domains in an integrated circuit

Techniques for operating a processor subsystem to service masked in...

Speedpath repair in an integrated circuit

State retention within a data processing system

Testing of data retention latches in circuit devices

State retention within a data processing system

Flip-flop circuit having low power data retention

Flip-flop circuit having low power data retention

Patents Applicationslast 30 patents

MANAGEMENT OF POWER DOMAINS IN AN INTEGRATED CIRCUIT

SPEEDPATH REPAIR IN AN INTEGRATED CIRCUIT

TECHNIQUES FOR OPERATING A PROCESSOR SUBSYSTEM

Testing of data retention latches in circuit devices

FLIP-FLOP CIRCUIT HAVING LOW POWER DATA RETENTION

Flip-flop circuit having low power data retention

State retention within a data processing system

State retention within a data processing system