Milind Sonawane

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performing testing utilizing staggered clocks
- Patent number 11,668,750
- Issue date Jun 6, 2023
- NVIDIA Corporation
- Sailendra Chadalavada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip execution of in-system test utilizing a generalized test image
- Patent number 10,890,620
- Issue date Jan 12, 2021
- NVIDIA Corp.
- Milind Bhaiyyasaheb Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Field adaptable in-system test mechanisms
- Patent number 10,746,798
- Issue date Aug 18, 2020
- NVIDIA Corp.
- Sailendra Chadalavada
- G01 - MEASURING TESTING
Information Patent Grant
Granular dynamic test systems and methods
- Patent number 10,545,189
- Issue date Jan 28, 2020
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Granular dynamic test systems and methods
- Patent number 10,481,203
- Issue date Nov 19, 2019
- NVIDIA Corporation
- Shantanu Sarangi
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic independent test partition clock
- Patent number 10,473,720
- Issue date Nov 12, 2019
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for dynamic standard test access (DSTA) for a log...
- Patent number 10,451,676
- Issue date Oct 22, 2019
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Independent test partition clock coordination across multiple test...
- Patent number 10,444,280
- Issue date Oct 15, 2019
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan system interface (SSI) module
- Patent number 10,317,463
- Issue date Jun 11, 2019
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test partition external input/output interface control for test par...
- Patent number 10,281,524
- Issue date May 7, 2019
- NVIDIA Corporation
- Sailendra Chadalavda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan systems and methods
- Patent number 9,885,753
- Issue date Feb 6, 2018
- NVIDIA Corporation
- Amit Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Performing on-chip partial good die identification
- Patent number 9,829,536
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
System for reducing peak power during scan shift at the local level...
- Patent number 9,395,414
- Issue date Jul 19, 2016
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
System for reducing peak power during scan shift at the global leve...
- Patent number 9,377,510
- Issue date Jun 28, 2016
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Global low power capture scheme for cores
- Patent number 9,222,981
- Issue date Dec 29, 2015
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PERFORMING TESTING UTILIZING STAGGERED CLOCKS
- Publication number 20230089800
- Publication date Mar 23, 2023
- NVIDIA Corporation
- Sailendra Chadalavada
- G01 - MEASURING TESTING
Information Patent Application
RUNTIME IN-SYSTEM TESTING
- Publication number 20220365857
- Publication date Nov 17, 2022
- NVIDIA Corporation
- Sailendra Chadalavada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP EXECUTION OF IN-SYSTEM TEST UTILIZING A GENERALIZED TEST IMAGE
- Publication number 20200363470
- Publication date Nov 19, 2020
- NVIDIA Corp.
- Milind Bhaiyyasaheb Sonawane
- G01 - MEASURING TESTING
Information Patent Application
PERFORMING ON-CHIP PARTIAL GOOD DIE IDENTIFICATION
- Publication number 20170219652
- Publication date Aug 3, 2017
- NVIDIA Corporation
- Milind SONAWANE
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170205465
- Publication date Jul 20, 2017
- NVIDIA Corporation
- Shantanu SARANGI
- G01 - MEASURING TESTING
Information Patent Application
TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL
- Publication number 20170115338
- Publication date Apr 27, 2017
- Sailendra Chadalavda
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC INDEPENDENT TEST PARTITION CLOCK
- Publication number 20170115351
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170115353
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEM INTERFACE (SSI) MODULE
- Publication number 20170115346
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...
- Publication number 20170115345
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...
- Publication number 20170115352
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEMS AND METHODS
- Publication number 20150100840
- Publication date Apr 9, 2015
- NVIDIA Corporation
- Amit SANGHANI
- G01 - MEASURING TESTING
Information Patent Application
GLOBAL LOW POWER CAPTURE SCHEME FOR CORES
- Publication number 20140189454
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVE...
- Publication number 20140189455
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE LOCAL LEVEL...
- Publication number 20140189452
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING

Milind Sonawane

Person

Patents Grantslast 30 patents

Performing testing utilizing staggered clocks

On-chip execution of in-system test utilizing a generalized test image

Field adaptable in-system test mechanisms

Granular dynamic test systems and methods

Granular dynamic test systems and methods

Dynamic independent test partition clock

Method and system for dynamic standard test access (DSTA) for a log...

Independent test partition clock coordination across multiple test...

Scan system interface (SSI) module

Test partition external input/output interface control for test par...

Scan systems and methods

Performing on-chip partial good die identification

System for reducing peak power during scan shift at the local level...

System for reducing peak power during scan shift at the global leve...

Global low power capture scheme for cores

Patents Applicationslast 30 patents

PERFORMING TESTING UTILIZING STAGGERED CLOCKS

RUNTIME IN-SYSTEM TESTING

ON-CHIP EXECUTION OF IN-SYSTEM TEST UTILIZING A GENERALIZED TEST IMAGE

PERFORMING ON-CHIP PARTIAL GOOD DIE IDENTIFICATION

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL

DYNAMIC INDEPENDENT TEST PARTITION CLOCK

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

SCAN SYSTEM INTERFACE (SSI) MODULE

METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...

INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...

SCAN SYSTEMS AND METHODS

GLOBAL LOW POWER CAPTURE SCHEME FOR CORES

SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVE...

SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE LOCAL LEVEL...