Milind Weling

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Nonvolatile resistive memory element with an oxygen-gettering layer
- Patent number 9,331,276
- Issue date May 3, 2016
- Intermolecular, Inc.
- Tony P. Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked bi-layer as the low power switchable RRAM
- Patent number 9,246,094
- Issue date Jan 26, 2016
- Intermolecular, Inc.
- Yun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doped narrow band gap nitrides for embedded resistors of resistive...
- Patent number 9,231,203
- Issue date Jan 5, 2016
- Intermolecular, Inc.
- Mihir Tendulkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Current-limiting electrodes
- Patent number 9,224,951
- Issue date Dec 29, 2015
- Intermolecular, Inc.
- Yun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile resistive memory element with an oxygen-gettering layer
- Patent number 8,981,332
- Issue date Mar 17, 2015
- Intermolecular, Inc.
- Tony P. Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive random access memory cells having doped current limiting...
- Patent number 8,912,518
- Issue date Dec 16, 2014
- Intermolecular, Inc.
- David Chi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of eliminating a lithography operation
- Patent number 8,716,135
- Issue date May 6, 2014
- Cadence Design Systems, Inc.
- Judy Huckabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for self-aligned doubled patterning lithography
- Patent number 8,679,981
- Issue date Mar 25, 2014
- Cadence Design Systems, Inc.
- Milind Weling
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of eliminating a lithography operation
- Patent number 8,656,321
- Issue date Feb 18, 2014
- Cadence Design Systems, Inc.
- Judy Huckabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of eliminating a lithography operation
- Patent number 8,440,569
- Issue date May 14, 2013
- Cadence Design Systems, Inc.
- Milind Weling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for self-aligned doubled patterning lithography
- Patent number 7,856,613
- Issue date Dec 21, 2010
- Cadence Design Systems, Inc.
- Milind Weling
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Customized polishing pad for selective process performance during c...
- Patent number 7,018,282
- Issue date Mar 28, 2006
- Koninklijke Philips Electronics N.V.
- Charles Franklin Drill
- B24 - GRINDING POLISHING
Information Patent Grant
Method of using films having optimized optical properties for chemi...
- Patent number 6,916,525
- Issue date Jul 12, 2005
- Koninklijke Philips Electronics N.V.
- Subhas Bothra
- B24 - GRINDING POLISHING
Information Patent Grant
Method of using films having optimized optical properties for chemi...
- Patent number 6,649,253
- Issue date Nov 18, 2003
- Koninklijke Philips Electronics N.V.
- Subhas Bothra
- B24 - GRINDING POLISHING
Information Patent Grant
Customized polishing pad for selective process performance during c...
- Patent number 6,572,439
- Issue date Jun 3, 2003
- Koninklijke Philips Electronics N.V.
- Charles Franklin Drill
- B24 - GRINDING POLISHING
Information Patent Grant
Methods for forming co-axial interconnect lines in a CMOS process f...
- Patent number 6,569,757
- Issue date May 27, 2003
- Philips Electronics North America Corporation
- Milind Weling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for implementing co-axial interconnect lines in a CMOS proc...
- Patent number 6,545,338
- Issue date Apr 8, 2003
- Koninklijke Philips Electronics N.V.
- Subhas Bothra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a gaseous environment providing improved c...
- Patent number 6,410,440
- Issue date Jun 25, 2002
- VLSI Technology, Inc.
- Charles F. Drill
- B24 - GRINDING POLISHING
Information Patent Grant
Waveguide structures integrated with standard CMOS circuitry and me...
- Patent number 6,387,720
- Issue date May 14, 2002
- Phillips Electronics North America Corporation
- Michael Misheloff
- G02 - OPTICS
Information Patent Grant
Gas phase planarization process for semiconductor wafers
- Patent number 6,380,092
- Issue date Apr 30, 2002
- VLSI Technology, Inc.
- Rao V. Annapragada
- B24 - GRINDING POLISHING
Information Patent Grant
Use of optimized film stacks for increasing absorption for laser re...
- Patent number 6,372,522
- Issue date Apr 16, 2002
- VLSI Technology, Inc.
- Milind Ganesh Weling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reducing interconnect resistance using an...
- Patent number 6,353,261
- Issue date Mar 5, 2002
- VLSI Technology, Inc.
- Milind Weling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacture of an integrated circuit isolation structure
- Patent number 6,319,796
- Issue date Nov 20, 2001
- VLSI Technology, Inc.
- Olivier Laparra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterned polishing pad for use in chemical mechanical polishing of...
- Patent number 6,315,645
- Issue date Nov 13, 2001
- VLSI Technology, Inc.
- Liming Zhang
- B24 - GRINDING POLISHING
Information Patent Grant
Semiconductor wafer, a chemical-mechanical alignment mark, and an a...
- Patent number 6,274,940
- Issue date Aug 14, 2001
- VLSI Technology, Inc.
- Daniel Claire Baker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gas phase planarization process for semiconductor wafers
- Patent number 6,267,076
- Issue date Jul 31, 2001
- VLSI Technology, Inc.
- Rao V. Annapragada
- B24 - GRINDING POLISHING
Information Patent Grant
Semiconductor dielectric structure and method for making the same
- Patent number 6,255,210
- Issue date Jul 3, 2001
- Philips Electronics North America Corp.
- Rao V. Annapragada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using a polish stop film to control dishing during copper...
- Patent number 6,242,805
- Issue date Jun 5, 2001
- VLSI Technology, Inc.
- Milind Weling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using films having optimized optical properties for chemi...
- Patent number 6,214,734
- Issue date Apr 10, 2001
- VLSI Technology, Inc.
- Subhas Bothra
- B24 - GRINDING POLISHING
Information Patent Grant
Chemical wet etch removal of underlayer material after performing c...
- Patent number 6,211,087
- Issue date Apr 3, 2001
- VLSI Technology, Inc.
- Calvin Gabriel
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CURRENT-LIMITING ELECTRODES
- Publication number 20160020392
- Publication date Jan 21, 2016
- INTERMOLECULAR INC.
- Yun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming current-programmable inline resistor
- Publication number 20150187841
- Publication date Jul 2, 2015
- INTERMOLECULAR INC.
- Yun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Bi-layer as the low power switchable RRAM
- Publication number 20150188045
- Publication date Jul 2, 2015
- INTERMOLECULAR INC.
- Yun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nonvolatile resistive memory element with an oxygen-gettering layer
- Publication number 20150155485
- Publication date Jun 4, 2015
- INTERMOLECULAR INC.
- Tony P. Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nonvolatile resistive memory element with an oxygen-gettering layer
- Publication number 20140268993
- Publication date Sep 18, 2014
- INTERMOLECULAR INC.
- Tony P. Chiang
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Random Access Memory Cells Having Doped Current Limiting...
- Publication number 20140124725
- Publication date May 8, 2014
- Intermolecular, Inc.
- David Chi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF ELIMINATING A LITHOGRAPHY OPERATION
- Publication number 20090146322
- Publication date Jun 11, 2009
- MILIND WELING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel Low Cost Implementation of a High Efficiency Solar Electric S...
- Publication number 20040139689
- Publication date Jul 22, 2004
- SUNLIT SYSTEMS
- Sunil Kumar Sinha
- F24 - HEATING RANGES VENTILATING
Information Patent Application
Method of using films having optimized optical properties for chemi...
- Publication number 20040058543
- Publication date Mar 25, 2004
- Subhas Bothra
- B24 - GRINDING POLISHING
Information Patent Application
Semiconductor dielectric structure and method for making the same
- Publication number 20010023989
- Publication date Sep 27, 2001
- PHILIPS ELECTRONICS NORTH AMERICA CORP.
- Rao V. Annapragada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus for improving alignment for metal masking
- Publication number 20010012674
- Publication date Aug 9, 2001
- Daniel Claire Baker
- H01 - BASIC ELECTRIC ELEMENTS

Milind Weling

Person

Patents Grantslast 30 patents

Nonvolatile resistive memory element with an oxygen-gettering layer

Stacked bi-layer as the low power switchable RRAM

Doped narrow band gap nitrides for embedded resistors of resistive...

Current-limiting electrodes

Nonvolatile resistive memory element with an oxygen-gettering layer

Resistive random access memory cells having doped current limiting...

Method of eliminating a lithography operation

Method for self-aligned doubled patterning lithography

Method of eliminating a lithography operation

Method of eliminating a lithography operation

Method for self-aligned doubled patterning lithography

Customized polishing pad for selective process performance during c...

Method of using films having optimized optical properties for chemi...

Method of using films having optimized optical properties for chemi...

Customized polishing pad for selective process performance during c...

Methods for forming co-axial interconnect lines in a CMOS process f...

Methods for implementing co-axial interconnect lines in a CMOS proc...

Method and apparatus for a gaseous environment providing improved c...

Waveguide structures integrated with standard CMOS circuitry and me...

Gas phase planarization process for semiconductor wafers

Use of optimized film stacks for increasing absorption for laser re...

Method and apparatus for reducing interconnect resistance using an...

Manufacture of an integrated circuit isolation structure

Patterned polishing pad for use in chemical mechanical polishing of...

Semiconductor wafer, a chemical-mechanical alignment mark, and an a...

Gas phase planarization process for semiconductor wafers

Semiconductor dielectric structure and method for making the same

Method of using a polish stop film to control dishing during copper...

Method of using films having optimized optical properties for chemi...

Chemical wet etch removal of underlayer material after performing c...

Patents Applicationslast 30 patents

CURRENT-LIMITING ELECTRODES

Method of forming current-programmable inline resistor

Stacked Bi-layer as the low power switchable RRAM

Nonvolatile resistive memory element with an oxygen-gettering layer

Nonvolatile resistive memory element with an oxygen-gettering layer

Resistive Random Access Memory Cells Having Doped Current Limiting...

METHOD OF ELIMINATING A LITHOGRAPHY OPERATION

Novel Low Cost Implementation of a High Efficiency Solar Electric S...

Method of using films having optimized optical properties for chemi...

Semiconductor dielectric structure and method for making the same

Apparatus for improving alignment for metal masking