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Fremont, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Automatic global clock tree synthesis
Patent number
11,836,000
Issue date
Dec 5, 2023
Synopsys, Inc.
Partha Das
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock network power estimation for logical designs
Patent number
11,526,642
Issue date
Dec 13, 2022
Synopsys, Inc.
Min Pan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Dual-structure clock tree synthesis (CTS)
Patent number
9,053,281
Issue date
Jun 9, 2015
Synopsys, Inc.
Xiaojun Ma
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
CIRCUIT DESIGN HAVING AN IMPROVED CLOCK TREE
Publication number
20230376670
Publication date
Nov 23, 2023
Synopsys, Inc.
Tao HUANG
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
SYSTEM FOR MAKING CIRCUIT DESIGN CHANGES
Publication number
20230334211
Publication date
Oct 19, 2023
Synopsys, Inc.
Zuo DAI
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
DUAL-STRUCTURE CLOCK TREE SYNTHESIS (CTS)
Publication number
20140289694
Publication date
Sep 25, 2014
Synopsys, Inc.
Xiaojun Ma
G06 - COMPUTING CALCULATING COUNTING