Ming-Hong Kuo

Person

Ping-Ting, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method to solve the dishing issue in CMP planarization by using a n...
- Patent number 6,261,923
- Issue date Jul 17, 2001
- Vanguard International Semiconductor Corporation
- Ming-Hong Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a capacitor under bit line DRAM structure usi...
- Patent number 6,184,081
- Issue date Feb 6, 2001
- Vanguard International Semiconductor Corporation
- Erik S. Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolator via non-critical chemical mechanical polishing
- Patent number 6,171,929
- Issue date Jan 9, 2001
- Vanguard International Semiconductor Corporation
- Fu-Liang Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design and a novel process for formation of DRAM bit line and capac...
- Patent number 6,133,599
- Issue date Oct 17, 2000
- Vanguard International Semiconductor Corporation
- Jan Mye Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate isolation by combining locos and shallow trench...
- Patent number 6,060,348
- Issue date May 9, 2000
- Vanguard International Semiconducter Corporation
- Fu-Liang Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a shallow trench isolation for ULSI formation via...
- Patent number 6,057,210
- Issue date May 2, 2000
- Vanguard International Semiconductor Corporation
- Fu-Liang Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a damascene landing pad
- Patent number 6,017,813
- Issue date Jan 25, 2000
- Vanguard International Semiconductor Corporation
- Ming-Hong Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design and a novel process for formation of DRAM bit line and capac...
- Patent number 6,008,085
- Issue date Dec 28, 1999
- Vanguard International Semiconductor Corporation
- Janmye Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Locos method with double polysilicon/silicon nitride spacer
- Patent number 5,658,822
- Issue date Aug 19, 1997
- Vanguard International Semiconductor Corporation
- Shye-Lin Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming nitride sidewalls having spacer feet in a locos p...
- Patent number 5,643,824
- Issue date Jul 1, 1997
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- H01 - BASIC ELECTRIC ELEMENTS

Ming-Hong Kuo

Person

Patents Grantslast 30 patents

Method to solve the dishing issue in CMP planarization by using a n...

Method of fabricating a capacitor under bit line DRAM structure usi...

Shallow trench isolator via non-critical chemical mechanical polishing

Design and a novel process for formation of DRAM bit line and capac...

Method to fabricate isolation by combining locos and shallow trench...

Method of making a shallow trench isolation for ULSI formation via...

Method for fabricating a damascene landing pad

Design and a novel process for formation of DRAM bit line and capac...

Locos method with double polysilicon/silicon nitride spacer

Method of forming nitride sidewalls having spacer feet in a locos p...