Mitsugi Ogura

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory device
- Patent number 5,095,463
- Issue date Mar 10, 1992
- Kabushiki Kaisha Toshiba
- Haruki Toda
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory system with dynamic random access memory cells
- Patent number 4,800,530
- Issue date Jan 24, 1989
- Kabushiki Kasiha Toshiba
- Yasuo Itoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices
- Patent number 4,799,193
- Issue date Jan 17, 1989
- Kabushiki Kaisha Toshiba
- Fumio Horiguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device with sense amplifiers
- Patent number 4,748,596
- Issue date May 31, 1988
- Kabushika Kaisha Toshiba
- Mitsugi Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for applying a voltage to a memory cell MOS capacitor of a...
- Patent number 4,725,985
- Issue date Feb 16, 1988
- Kabushiki Kaisha Toshiba
- Mitsugi Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having error detection/correction function
- Patent number 4,706,249
- Issue date Nov 10, 1987
- Kabushiki Kaisha Toshiba
- Kaoru Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory clock pulse generating circuit with reduced peak current req...
- Patent number 4,644,184
- Issue date Feb 17, 1987
- Tokyo Shibaura Denki Kabushiki Kaisha
- Naokazu Miyawaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having a voltage push-up circuit
- Patent number 4,636,981
- Issue date Jan 13, 1987
- Tokyo Shibaura Denki Kabushiki Kaisha
- Mitsugi Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
MOS Decoder selection circuit having a barrier transistor whose non...
- Patent number 4,490,628
- Issue date Dec 25, 1984
- Tokyo Shibaura Denki Kabushiki Kaisha
- Mitsugi Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of evaluating measure precision of patterns and photomask th...
- Patent number 4,433,911
- Issue date Feb 28, 1984
- Tokyo Shibaura Denki Kabushiki Kaisha
- Shizuo Sawada
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Mitsugi Ogura

Person

Patents Grantslast 30 patents

Semiconductor memory device

Semiconductor memory system with dynamic random access memory cells

Semiconductor memory devices

Semiconductor memory device with sense amplifiers

Circuit for applying a voltage to a memory cell MOS capacitor of a...

Semiconductor memory device having error detection/correction function

Memory clock pulse generating circuit with reduced peak current req...

Semiconductor memory device having a voltage push-up circuit

MOS Decoder selection circuit having a barrier transistor whose non...

Method of evaluating measure precision of patterns and photomask th...