Mohamed R. SABER

Person

College Station, TX, US

People

Patents Applicationslast 30 patents

Information Patent Application
VERTICALLY EMBEDDED COMPONENTS IN PACKAGE SUBSTRATES
- Publication number 20250219021
- Publication date Jul 3, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Technologies for Components Embedded in a Substrate Core
- Publication number 20250219040
- Publication date Jul 3, 2025
- Intel Corporation
- Tolga ACIKALIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY EMBEDDED UTILITY PATCH FOR SEMICONDUCTOR PACKAGES
- Publication number 20250210491
- Publication date Jun 26, 2025
- Intel Corporation
- Mohamed R. Saber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PASSIVE STRUCTURES IN EMBEDDED BRIDGE ARCHITECTURES
- Publication number 20250183179
- Publication date Jun 5, 2025
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH EDGE STRESS REDUCTION IN GLASS CORES
- Publication number 20250112175
- Publication date Apr 3, 2025
- Intel Corporation
- Brandon C. Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL IS...
- Publication number 20250112144
- Publication date Apr 3, 2025
- Intel Corporation
- Mohamed R. Saber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED THERMAL HEALING AND DOPING OF GLASS CORES FOR MICROELECTR...
- Publication number 20250096052
- Publication date Mar 20, 2025
- Intel Corporation
- Mohamed R. Saber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW STRESS THROUGH GLASS VIAS (TGVS)
- Publication number 20250089156
- Publication date Mar 13, 2025
- Intel Corporation
- Mohamed R. SABER
- H01 - BASIC ELECTRIC ELEMENTS

Mohamed R. SABER

Person

Patents Applicationslast 30 patents

VERTICALLY EMBEDDED COMPONENTS IN PACKAGE SUBSTRATES

Technologies for Components Embedded in a Substrate Core

VERTICALLY EMBEDDED UTILITY PATCH FOR SEMICONDUCTOR PACKAGES

PASSIVE STRUCTURES IN EMBEDDED BRIDGE ARCHITECTURES

MICROELECTRONIC ASSEMBLIES WITH EDGE STRESS REDUCTION IN GLASS CORES

INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL IS...

LOCALIZED THERMAL HEALING AND DOPING OF GLASS CORES FOR MICROELECTR...

LOW STRESS THROUGH GLASS VIAS (TGVS)