Mohammad Mortazavi

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Transistor-level timing analysis using embedded simulation
- Patent number 7,647,220
- Issue date Jan 12, 2010
- Cadence Design Systems, Inc.
- Pawan Kulshreshtha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional timing analysis for characterization of virtual componen...
- Patent number 7,346,872
- Issue date Mar 18, 2008
- Cadence Design Systems, Inc.
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for timing abstraction of digital logic circuits
- Patent number 6,877,143
- Issue date Apr 5, 2005
- Cadence Design Systems, Inc.
- Robert J Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for performing improved timing analysis on vir...
- Patent number 6,760,894
- Issue date Jul 6, 2004
- Cadence Design Systems, Inc.
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional timing analysis for characterization of virtual componen...
- Patent number 6,457,159
- Issue date Sep 24, 2002
- Cadence Design Systems, Inc.
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for timing abstraction of digital logic circuits
- Patent number 6,442,739
- Issue date Aug 27, 2002
- Cadence Design Systems, Inc.
- Robert J. Palermo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Functional timing analysis for characterization of virtual componen...
- Publication number 20030140324
- Publication date Jul 24, 2003
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transistor-level timing analysis using embedded simulation
- Publication number 20030115035
- Publication date Jun 19, 2003
- Pawan Kulshreshtha
- G06 - COMPUTING CALCULATING COUNTING