Mohan R. Nagar

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Milpitas, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Measurement of package interconnect impedance using tester and supp...
- Patent number 6,946,866
- Issue date Sep 20, 2005
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Grant
Substrate impedance measurement
- Patent number 6,891,392
- Issue date May 10, 2005
- LSI Logic Corporation
- Mohan R. Nagar
- G01 - MEASURING TESTING
Information Patent Grant
Substrate impedance measurement
- Patent number 6,717,423
- Issue date Apr 6, 2004
- LSI Logic Corporation
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Grant
Reducing probe card substrate warpage
- Patent number 6,605,954
- Issue date Aug 12, 2003
- LSI Logic Corporation
- Mohan R. Nagar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Measurement of package interconnect impedance using tester and supp...
- Publication number 20040251925
- Publication date Dec 16, 2004
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING
Information Patent Application
Novel solution for low cost, speedy probe cards
- Publication number 20040239350
- Publication date Dec 2, 2004
- Mohan R. Nagar
- G01 - MEASURING TESTING
Information Patent Application
Substrate impedance measurement
- Publication number 20040164758
- Publication date Aug 26, 2004
- Mohan R. Nagar
- G01 - MEASURING TESTING
Information Patent Application
SUBSTRATE IMPEDANCE MEASUREMENT
- Publication number 20040070402
- Publication date Apr 15, 2004
- Aritharan Thurairajaratnam
- G01 - MEASURING TESTING