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Mohan Tandyala
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San Jose, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Multiplexer reduction for programmable logic devices
Patent number
10,027,328
Issue date
Jul 17, 2018
LATTICE SEMICONDUCTOR CORPORATION
Sunil Sharma
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Early global set/reset signal determination for programmable logic...
Patent number
9,680,475
Issue date
Jun 13, 2017
LATTICE SEMICONDUCTOR CORPORATION
Venkatesan Rajappan
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Grant
Partition based design implementation for programmable logic devices
Patent number
9,449,133
Issue date
Sep 20, 2016
LATTICE SEMICONDUCTOR CORPORATION
Hua Xue
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Logic absorption techniques for programmable logic devices
Patent number
9,390,210
Issue date
Jul 12, 2016
LATTICE SEMICONDUCTOR CORPORATION
Nilanjan Chatterjee
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
MULTIPLEXER REDUCTION FOR PROGRAMMABLE LOGIC DEVICES
Publication number
20170272077
Publication date
Sep 21, 2017
Lattice Semiconductor Corporation
Sunil Sharma
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
LOGIC ABSORPTION TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES
Publication number
20150347642
Publication date
Dec 3, 2015
Lattice Semiconductor Corporation
Nilanjan Chatterjee
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
PARTITION BASED DESIGN IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES
Publication number
20150324509
Publication date
Nov 12, 2015
Lattice Semiconductor Corporation
Hua Xue
G06 - COMPUTING CALCULATING COUNTING