Mu-Tien CHANG

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bandwidth boosted stacked memory
- Patent number 12,248,402
- Issue date Mar 11, 2025
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 12,242,344
- Issue date Mar 4, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D-stacked memory with reconfigurable compute logic
- Patent number 12,197,726
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 12,189,546
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 12,147,360
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated in-module RAS features for synchronous DDR compatible m...
- Patent number 12,032,828
- Issue date Jul 9, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ISA extension for high-bandwidth memory
- Patent number 11,940,922
- Issue date Mar 26, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D-stacked memory with reconfigurable compute logic
- Patent number 11,789,610
- Issue date Oct 17, 2023
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 11,625,296
- Issue date Apr 11, 2023
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual row-column major dram
- Patent number 11,568,920
- Issue date Jan 31, 2023
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ISA extension for high-bandwidth memory
- Patent number 11,556,476
- Issue date Jan 17, 2023
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth boosted stacked memory
- Patent number 11,513,965
- Issue date Nov 29, 2022
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 11,397,698
- Issue date Jul 26, 2022
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated in-module RAS features for synchronous DDR compatible m...
- Patent number 11,294,571
- Issue date Apr 5, 2022
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for write and flush support in hybrid memory
- Patent number 11,175,853
- Issue date Nov 16, 2021
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3-D stacked memory with reconfigurable compute logic
- Patent number 11,079,936
- Issue date Aug 3, 2021
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page size synchronization and page size aware scheduling method for...
- Patent number 11,029,879
- Issue date Jun 8, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 11,010,242
- Issue date May 18, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 10,977,118
- Issue date Apr 13, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cell structure for non-volatile resistive memory
- Patent number 10,929,026
- Issue date Feb 23, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth boosted stacked memory
- Patent number 10,915,451
- Issue date Feb 9, 2021
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to deliver in-DRAM ECC information through DDR bus
- Patent number 10,908,993
- Issue date Feb 2, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to deliver in-DRAM ECC information through DDR bus
- Patent number 10,872,014
- Issue date Dec 22, 2020
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ISA extension for high-bandwidth memory
- Patent number 10,866,900
- Issue date Dec 15, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Byte-addressable flash-based memory module with prefetch mode that...
- Patent number 10,866,897
- Issue date Dec 15, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of executing conditional data scrubbing inside a smart stora...
- Patent number 10,824,348
- Issue date Nov 3, 2020
- Samsung Electronics Co., Ltd.
- Sompong Paul Olarig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for operating a DRR-compatible asynchronous memor...
- Patent number 10,810,144
- Issue date Oct 20, 2020
- Samsung Electronics Co., Ltd.
- Sun Young Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to deliver in-DRAM ECC information through DDR bus
- Patent number 10,795,764
- Issue date Oct 6, 2020
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND...
- Patent number 10,762,000
- Issue date Sep 1, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dedupe DRAM cache
- Patent number 10,705,969
- Issue date Jul 7, 2020
- Samsung Electronics Co., Ltd.
- Mu Tien Chang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20250036584
- Publication date Jan 30, 2025
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20240143173
- Publication date May 2, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC
- Publication number 20240004547
- Publication date Jan 4, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20230229555
- Publication date Jul 20, 2023
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY
- Publication number 20230119291
- Publication date Apr 20, 2023
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BANDWIDTH BOOSTED STACKED MEMORY
- Publication number 20230087747
- Publication date Mar 23, 2023
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20220358060
- Publication date Nov 10, 2022
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20220229551
- Publication date Jul 21, 2022
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC
- Publication number 20210311634
- Publication date Oct 7, 2021
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20210294697
- Publication date Sep 23, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BANDWIDTH BOOSTED STACKED MEMORY
- Publication number 20210141735
- Publication date May 13, 2021
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY
- Publication number 20210096999
- Publication date Apr 1, 2021
- SAMSUNG ELECTRONICS CO., LTD.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BANDWIDTH BOOSTED STACKED MEMORY
- Publication number 20200356488
- Publication date Nov 12, 2020
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20200218447
- Publication date Jul 9, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20200167297
- Publication date May 28, 2020
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO DELIVER IN-DRAM ECC INFORMATION THROUGH DDR BUS
- Publication number 20190266050
- Publication date Aug 29, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO DELIVER IN-DRAM ECC INFORMATION THROUGH DDR BUS
- Publication number 20190266049
- Publication date Aug 29, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE SIZE SYNCHRONIZATION AND PAGE SIZE AWARE SCHEDULING METHOD FOR...
- Publication number 20190235788
- Publication date Aug 1, 2019
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEDUPE DRAM CACHE
- Publication number 20190227941
- Publication date Jul 25, 2019
- Samsung Electronics Co., Ltd.
- Mu Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20190179704
- Publication date Jun 13, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20190179705
- Publication date Jun 13, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY
- Publication number 20190114265
- Publication date Apr 18, 2019
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL ROW-COLUMN MAJOR DRAM
- Publication number 20190043553
- Publication date Feb 7, 2019
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED NEAR-FAR MEMORY CONTROLLER FOR PROCESS-IN-HBM
- Publication number 20190034097
- Publication date Jan 31, 2019
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY
- Publication number 20180329651
- Publication date Nov 15, 2018
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MORPHABLE ECC ENCODER/DECODER FOR NVDIMM OVER DDR CHANNEL
- Publication number 20180322007
- Publication date Nov 8, 2018
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO REDUCE READ-MODIFY-WRITE OVERHEAD IN HYBRID DRAM/NAND...
- Publication number 20180293175
- Publication date Oct 11, 2018
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID DRAM ARRAY INCLUDING DISSIMILAR MEMORY CELLS
- Publication number 20180285253
- Publication date Oct 4, 2018
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING DRAM CACHE METADATA ACCESS OVERHEAD WITH SRAM METADATA C...
- Publication number 20180232310
- Publication date Aug 16, 2018
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH AWARE REPLACEMENT POLICY FOR VOLATILE MEMORY CACHE
- Publication number 20180210843
- Publication date Jul 26, 2018
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING

Mu-Tien CHANG

Person

Patents Grantslast 30 patents

Bandwidth boosted stacked memory

DRAM assist error correction mechanism for DDR SDRAM interface

3D-stacked memory with reconfigurable compute logic

Asynchronous communication protocol compatible with synchronous DDR...

Asynchronous communication protocol compatible with synchronous DDR...

Coordinated in-module RAS features for synchronous DDR compatible m...

ISA extension for high-bandwidth memory

3D-stacked memory with reconfigurable compute logic

DRAM assist error correction mechanism for DDR SDRAM interface

Dual row-column major dram

ISA extension for high-bandwidth memory

Bandwidth boosted stacked memory

Asynchronous communication protocol compatible with synchronous DDR...

Coordinated in-module RAS features for synchronous DDR compatible m...

Systems and methods for write and flush support in hybrid memory

3-D stacked memory with reconfigurable compute logic

Page size synchronization and page size aware scheduling method for...

DRAM assist error correction mechanism for DDR SDRAM interface

DRAM assist error correction mechanism for DDR SDRAM interface

Multi-cell structure for non-volatile resistive memory

Bandwidth boosted stacked memory

Method to deliver in-DRAM ECC information through DDR bus

Method to deliver in-DRAM ECC information through DDR bus

ISA extension for high-bandwidth memory

Byte-addressable flash-based memory module with prefetch mode that...

Method of executing conditional data scrubbing inside a smart stora...

System and method for operating a DRR-compatible asynchronous memor...

Method to deliver in-DRAM ECC information through DDR bus

Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND...

Dedupe DRAM cache

Patents Applicationslast 30 patents

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY

BANDWIDTH BOOSTED STACKED MEMORY

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

3D-STACKED MEMORY WITH RECONFIGURABLE COMPUTE LOGIC

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

BANDWIDTH BOOSTED STACKED MEMORY

ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY

BANDWIDTH BOOSTED STACKED MEMORY

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

METHOD TO DELIVER IN-DRAM ECC INFORMATION THROUGH DDR BUS

METHOD TO DELIVER IN-DRAM ECC INFORMATION THROUGH DDR BUS

PAGE SIZE SYNCHRONIZATION AND PAGE SIZE AWARE SCHEDULING METHOD FOR...

DEDUPE DRAM CACHE

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

ISA EXTENSION FOR HIGH-BANDWIDTH MEMORY

DUAL ROW-COLUMN MAJOR DRAM

COORDINATED NEAR-FAR MEMORY CONTROLLER FOR PROCESS-IN-HBM

SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY

MORPHABLE ECC ENCODER/DECODER FOR NVDIMM OVER DDR CHANNEL

TECHNIQUES TO REDUCE READ-MODIFY-WRITE OVERHEAD IN HYBRID DRAM/NAND...

HYBRID DRAM ARRAY INCLUDING DISSIMILAR MEMORY CELLS

MITIGATING DRAM CACHE METADATA ACCESS OVERHEAD WITH SRAM METADATA C...

REFRESH AWARE REPLACEMENT POLICY FOR VOLATILE MEMORY CACHE