Mukund Narasimhan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Aging mitigation
- Patent number 11,971,741
- Issue date Apr 30, 2024
- QUALCOMM Incorporated
- Mukund Narasimhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with high-speed and area-efficient read path
- Patent number 11,315,609
- Issue date Apr 26, 2022
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power and high-density core-power lowering for memory write assist
- Patent number 11,074,967
- Issue date Jul 27, 2021
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G05 - CONTROLLING REGULATING
Information Patent Grant
Area efficient write data path circuit for SRAM yield enhancement
- Patent number 10,867,668
- Issue date Dec 15, 2020
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with high-speed and area-efficient read path
- Patent number 10,854,246
- Issue date Dec 1, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power and high-density core-power lowering for memory write assist
- Patent number 10,832,764
- Issue date Nov 10, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flexible power sequencing for dual-power memory
- Patent number 10,446,196
- Issue date Oct 15, 2019
- QUALCOMM Incorporated
- Mukund Narasimhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Robust write driver scheme for static random access memory compilers
- Patent number 10,147,483
- Issue date Dec 4, 2018
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Noise immune data path scheme for multi-bank memory architecture
- Patent number 10,140,224
- Issue date Nov 27, 2018
- QUALCOMM Incorporated
- Mukund Narasimhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitline precharge control and tracking scheme providing increased m...
- Patent number 9,928,889
- Issue date Mar 27, 2018
- Qualcomm Incorporation
- Mukund Narasimhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Write driver circuitry to reduce leakage of negative boost charge
- Patent number 9,916,892
- Issue date Mar 13, 2018
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Write data path to reduce charge leakage of negative boost
- Patent number 9,865,337
- Issue date Jan 9, 2018
- QUALCOMM Incorporated
- Fahad Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a word line assertion delayed by a bit line discharge f...
- Patent number 9,865,316
- Issue date Jan 9, 2018
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for controlling boost capacitance for low powe...
- Patent number 9,837,144
- Issue date Dec 5, 2017
- QUALCOMM Incorporated
- Rakesh Kumar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse latch reset tracking at high differential voltage
- Patent number 9,607,674
- Issue date Mar 28, 2017
- QUALCOMM Incorporated
- Mukund Narasimhan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
AGING MITIGATION
- Publication number 20230038670
- Publication date Feb 9, 2023
- QUALCOMM Incorporated
- Mukund NARASIMHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH
- Publication number 20210020206
- Publication date Jan 21, 2021
- Qualcomm Incorporated
- Adithya BHASKARAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
- Publication number 20210020234
- Publication date Jan 21, 2021
- Qualcomm Incorporated
- Adithya BHASKARAN
- G05 - CONTROLLING REGULATING
Information Patent Application
Memory with High-Speed and Area-Efficient Read Path
- Publication number 20200372939
- Publication date Nov 26, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
- Publication number 20200251163
- Publication date Aug 6, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
- Publication number 20190108872
- Publication date Apr 11, 2019
- QUALCOMM Incorporated
- Sharad Kumar GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE
- Publication number 20180113821
- Publication date Apr 26, 2018
- QUALCOMM Incorporated
- Mukund NARASIMHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH IMPROVED WRITE TIME AND REDUCED WRITE POWER
- Publication number 20170213587
- Publication date Jul 27, 2017
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE

Mukund Narasimhan

Person

Patents Grantslast 30 patents

Aging mitigation

Memory with high-speed and area-efficient read path

Low-power and high-density core-power lowering for memory write assist

Area efficient write data path circuit for SRAM yield enhancement

Memory with high-speed and area-efficient read path

Low-power and high-density core-power lowering for memory write assist

Flexible power sequencing for dual-power memory

Robust write driver scheme for static random access memory compilers

Noise immune data path scheme for multi-bank memory architecture

Bitline precharge control and tracking scheme providing increased m...

Write driver circuitry to reduce leakage of negative boost charge

Write data path to reduce charge leakage of negative boost

Memory with a word line assertion delayed by a bit line discharge f...

Apparatus and method for controlling boost capacitance for low powe...

Pulse latch reset tracking at high differential voltage

Patents Applicationslast 30 patents

AGING MITIGATION

MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH

LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST

Memory with High-Speed and Area-Efficient Read Path

LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST

AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT

NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE

MEMORY WITH IMPROVED WRITE TIME AND REDUCED WRITE POWER