Munenobu Kida

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Tokyo, JP

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device having a multilayered wiring structure
- Patent number 5,402,005
- Issue date Mar 28, 1995
- Kabushiki Kaisha Toshiba
- Kohichi Takayama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Master-slave clocked CMOS flip-flop with hysteresis
- Patent number 5,107,137
- Issue date Apr 21, 1992
- Kabushiki Kaisha Toshiba
- Masanori Kinugasa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output control circuit for reducing through current in CMOS output...
- Patent number 5,034,629
- Issue date Jul 23, 1991
- Kabushiki Kaisha Toshiba
- Masanori Kinugasa
- H03 - BASIC ELECTRONIC CIRCUITRY