MURALI V R M. KOTA

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SHRUB OAK, NY, US

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Patents Grantslast 30 patents

Information Patent Grant
Logic layout with reduced area and method of making the same
- Patent number 10,373,942
- Issue date Aug 6, 2019
- GLOBALFOUNDRIES Inc.
- Ram Asra
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOGIC LAYOUT WITH REDUCED AREA AND METHOD OF MAKING THE SAME
- Publication number 20190172822
- Publication date Jun 6, 2019
- GLOBALFOUNDRIES INC.
- Ram ASRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TUNNEL FINFET WITH SELF-ALIGNED GATE
- Publication number 20180254340
- Publication date Sep 6, 2018
- GLOBALFOUNDRIES INC.
- EDWARD J. NOWAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TUNNEL FINFET WITH SELF-ALIGNED GATE
- Publication number 20180138307
- Publication date May 17, 2018
- GLOBALFOUNDRIES INC.
- EDWARD J. NOWAK
- H01 - BASIC ELECTRIC ELEMENTS