Muriel Martinez

Person

Saint Egreve, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Germanium layer polishing
- Patent number 8,304,345
- Issue date Nov 6, 2012
- Soitec
- Muriel Martinez
- B24 - GRINDING POLISHING
Information Patent Grant
Planarization of a heteroepitaxial layer
- Patent number 7,718,534
- Issue date May 18, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Muriel Martinez
- B24 - GRINDING POLISHING
Information Patent Grant
Substrate layer cutting device and method
- Patent number 7,406,994
- Issue date Aug 5, 2008
- S.O.I. Tec Silicon on Insulator Technologies
- Muriel Martinez
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Grant
Semiconductor structure and method of making same
- Patent number 7,391,094
- Issue date Jun 24, 2008
- S.O.I. Tec Silicon on Insulator Technologies
- Olivier Rayssac
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate layer cutting device and method
- Patent number 7,189,304
- Issue date Mar 13, 2007
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Muriel Martinez
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Grant
Semiconductor structure and method of making same
- Patent number 6,989,314
- Issue date Jan 24, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Olivier Rayssac
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing a heterogeneous semiconductor structure
- Patent number 6,858,517
- Issue date Feb 22, 2005
- S.O.I.Tec Silicon on Insulator Technologies S.A.
- Muriel Martinez
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR POLISHING HETEROSTRUCTURES
- Publication number 20110117740
- Publication date May 19, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Muriel Martinez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GERMANIUM LAYER POLISHING
- Publication number 20110045654
- Publication date Feb 24, 2011
- S.O.I.T.E.C. SILICON ON INSULATOR TECHNOLOGIES
- Muriel Martinez
- B24 - GRINDING POLISHING
Information Patent Application
SUBSTRATE LAYER CUTTING DEVICE AND METHOD
- Publication number 20070122926
- Publication date May 31, 2007
- S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.
- Muriel Martinez
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Application
PLANARIZATION OF A HETEROEPITAXIAL LAYER
- Publication number 20070087570
- Publication date Apr 19, 2007
- Muriel Martinez
- B24 - GRINDING POLISHING
Information Patent Application
Semiconductor structure and method of making same
- Publication number 20060086949
- Publication date Apr 27, 2006
- S.O.I.Tec Silicon on Insulator Technologies S.A., a French company
- Olivier Rayssac
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF PRODUCING A HETEROGENEOUS SEMICONDUCTOR STRUCTURE
- Publication number 20040253795
- Publication date Dec 16, 2004
- Muriel Martinez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrate layer cutting device and method
- Publication number 20040144487
- Publication date Jul 29, 2004
- Muriel Martinez
- B28 - WORKING CEMENT, CLAY, OR STONE

Muriel Martinez

Person

Patents Grantslast 30 patents

Germanium layer polishing

Planarization of a heteroepitaxial layer

Substrate layer cutting device and method

Semiconductor structure and method of making same

Substrate layer cutting device and method

Semiconductor structure and method of making same

Methods of producing a heterogeneous semiconductor structure

Patents Applicationslast 30 patents

METHOD FOR POLISHING HETEROSTRUCTURES

GERMANIUM LAYER POLISHING

SUBSTRATE LAYER CUTTING DEVICE AND METHOD

PLANARIZATION OF A HETEROEPITAXIAL LAYER

Semiconductor structure and method of making same

METHODS OF PRODUCING A HETEROGENEOUS SEMICONDUCTOR STRUCTURE

Substrate layer cutting device and method