Muthurajan Jayakumar

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Mechanism for efficiently processing deferred order-dependent memor...
- Patent number RE40921
- Issue date Sep 22, 2009
- Intel Corporation
- William S. Wu
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Apparatus and method for initiating hardware priority management by...
- Patent number 6,298,410
- Issue date Oct 2, 2001
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting and compensating for certain sno...
- Patent number 6,292,906
- Issue date Sep 18, 2001
- Intel Corporation
- John W. C. Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing out-of-order bus operations in...
- Patent number 6,260,091
- Issue date Jul 10, 2001
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bootstrap processor selection architecture in SMP system
- Patent number 6,108,781
- Issue date Aug 22, 2000
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling multiple level-triggered and edge...
- Patent number 6,021,458
- Issue date Feb 1, 2000
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bus operations in a computer sy...
- Patent number 6,012,118
- Issue date Jan 4, 2000
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for data strobe pre-driving during master changeover on a...
- Patent number 5,964,856
- Issue date Oct 12, 1999
- Intel Corporation
- William S. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for efficiently processing deferred order-dependent memor...
- Patent number 5,961,621
- Issue date Oct 5, 1999
- Intel Corporation
- William S. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for tracking bus transactions
- Patent number 5,951,663
- Issue date Sep 14, 1999
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bootstrap processor selection architecture in SMP systems
- Patent number 5,904,733
- Issue date May 18, 1999
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation of interrupt control mechanism in a multiprocessor system
- Patent number 5,889,978
- Issue date Mar 30, 1999
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for delivering interrupt messages
- Patent number 5,848,279
- Issue date Dec 8, 1998
- Intel Corporation
- William S. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing an enhanced programmable priorit...
- Patent number 5,511,200
- Issue date Apr 23, 1996
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for providing programmable interrupts for embedded hardware...
- Patent number 5,481,725
- Issue date Jan 2, 1996
- Intel Corporation
- Muthurajan Jayakumar
- G06 - COMPUTING CALCULATING COUNTING

Muthurajan Jayakumar

Person

Patents Grantslast 30 patents

Mechanism for efficiently processing deferred order-dependent memor...

Apparatus and method for initiating hardware priority management by...

Method and apparatus for detecting and compensating for certain sno...

Method and apparatus for performing out-of-order bus operations in...

Bootstrap processor selection architecture in SMP system

Method and apparatus for handling multiple level-triggered and edge...

Method and apparatus for performing bus operations in a computer sy...

Mechanism for data strobe pre-driving during master changeover on a...

Mechanism for efficiently processing deferred order-dependent memor...

Method and apparatus for tracking bus transactions

Bootstrap processor selection architecture in SMP systems

Emulation of interrupt control mechanism in a multiprocessor system

Mechanism for delivering interrupt messages

Method and apparatus for providing an enhanced programmable priorit...

Method for providing programmable interrupts for embedded hardware...