Mutsunori Igarashi

Person

Kanagawa-ken, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Computer implemented design system, a computer implemented design m...
- Patent number 7,539,952
- Issue date May 26, 2009
- Kabushiki Kaisha Toshiba
- Atsushi Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Patent number 7,230,554
- Issue date Jun 12, 2007
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Computer implemented design system, a computer implemented design m...
- Patent number 7,127,694
- Issue date Oct 24, 2006
- Kabushiki Kaisha Toshiba
- Atsushi Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated wiring pattern layout method
- Patent number 7,124,389
- Issue date Oct 17, 2006
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Patent number 7,064,691
- Issue date Jun 20, 2006
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout design system, layout design method and layout design progra...
- Patent number 7,013,444
- Issue date Mar 14, 2006
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and program for designing a semiconductor integra...
- Patent number 6,904,572
- Issue date Jun 7, 2005
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,813,756
- Issue date Nov 2, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern correction method, apparatus, and program
- Patent number 6,792,593
- Issue date Sep 14, 2004
- Kabushiki Kaisha Toshiba
- Makoto Takashima
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Automated wiring pattern layout method
- Patent number 6,779,167
- Issue date Aug 17, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout design system, layout design method and layout design progra...
- Patent number 6,763,508
- Issue date Jul 13, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTI...
- Patent number 6,683,336
- Issue date Jan 27, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,645,842
- Issue date Nov 11, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,546,540
- Issue date Apr 8, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise suppression circuit, ASIC, navigation apparatus communication...
- Patent number 6,459,331
- Issue date Oct 1, 2002
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,436,804
- Issue date Aug 20, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,262,487
- Issue date Jul 17, 2001
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit and supply method for supplying mu...
- Patent number 6,097,043
- Issue date Aug 1, 2000
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit of low power consumption type
- Patent number 5,986,961
- Issue date Nov 16, 1999
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout method of wiring pattern for semiconductor integrated circuit
- Patent number 5,801,960
- Issue date Sep 1, 1998
- Kabushiki Kaisha Toshiba
- Midori Takano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for arranging logical cells in a semiconductor integrated ci...
- Patent number 5,397,749
- Issue date Mar 14, 1995
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement method for logic cells in semiconductor IC device
- Patent number 5,224,057
- Issue date Jun 29, 1993
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Computer implemented design system, a computer implemented design m...
- Publication number 20070011638
- Publication date Jan 11, 2007
- Kabushiki Kaisha Toshiba
- Atsushi Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Noise suppression circuit, ASIC, navigation apparatus, communicatio...
- Publication number 20060197695
- Publication date Sep 7, 2006
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Computer implemented design system, a computer implemented design m...
- Publication number 20050166176
- Publication date Jul 28, 2005
- Atsushi Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit device, clock layout system, clock layout method...
- Publication number 20040237060
- Publication date Nov 25, 2004
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated wiring pattern layout method
- Publication number 20040210862
- Publication date Oct 21, 2004
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout design system, layout design method and layout design progra...
- Publication number 20040199892
- Publication date Oct 7, 2004
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus and program for designing a semiconductor integra...
- Publication number 20030167451
- Publication date Sep 4, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automatic layout design for LSI, mask set and semiconduct...
- Publication number 20030079194
- Publication date Apr 24, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Noise suppression circuit, asic, navigation apparatus, communicatio...
- Publication number 20030011500
- Publication date Jan 16, 2003
- Kabushiki Kaisha Toshiba
- Hideki Takeuchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pattern correction method, apparatus, and program
- Publication number 20030005390
- Publication date Jan 2, 2003
- Makoto Takashima
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Layout design system, layout design method and layout design progra...
- Publication number 20030005399
- Publication date Jan 2, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20020182844
- Publication date Dec 5, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Automated wiring pattern layout method
- Publication number 20020162079
- Publication date Oct 31, 2002
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20010011776
- Publication date Aug 9, 2001
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS

Mutsunori Igarashi

Person

Patents Grantslast 30 patents

Computer implemented design system, a computer implemented design m...

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Computer implemented design system, a computer implemented design m...

Automated wiring pattern layout method

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Layout design system, layout design method and layout design progra...

Method, apparatus and program for designing a semiconductor integra...

Method of automatic layout design for LSI, mask set and semiconduct...

Pattern correction method, apparatus, and program

Automated wiring pattern layout method

Layout design system, layout design method and layout design progra...

SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTI...

Semiconductor integrated circuit device, semiconductor integrated c...

Method of automatic layout design for LSI, mask set and semiconduct...

Noise suppression circuit, ASIC, navigation apparatus communication...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit and supply method for supplying mu...

Semiconductor integrated circuit of low power consumption type

Layout method of wiring pattern for semiconductor integrated circuit

Method for arranging logical cells in a semiconductor integrated ci...

Arrangement method for logic cells in semiconductor IC device

Patents Applicationslast 30 patents

Computer implemented design system, a computer implemented design m...

Noise suppression circuit, ASIC, navigation apparatus, communicatio...

Computer implemented design system, a computer implemented design m...

Integrated circuit device, clock layout system, clock layout method...

Automated wiring pattern layout method

Layout design system, layout design method and layout design progra...

Method, apparatus and program for designing a semiconductor integra...

Method of automatic layout design for LSI, mask set and semiconduct...

Noise suppression circuit, asic, navigation apparatus, communicatio...

Pattern correction method, apparatus, and program

Layout design system, layout design method and layout design progra...

Semiconductor integrated circuit device, semiconductor integrated c...

Automated wiring pattern layout method

Semiconductor integrated circuit device, semiconductor integrated c...