Nadav Bonen

Person

Ofer, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Memory power management method and apparatus
- Patent number 12,165,686
- Issue date Dec 10, 2024
- Intel Corporation
- Nivedha Krishnakumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-tenant cryptographic memory isolation
- Patent number 11,687,681
- Issue date Jun 27, 2023
- Intel Corporation
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management to improve power performance
- Patent number 11,520,498
- Issue date Dec 6, 2022
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for dynamic transformation of memory configuration
- Patent number 10,877,693
- Issue date Dec 29, 2020
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing local power gating in a processor
- Patent number 10,802,567
- Issue date Oct 13, 2020
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tenant cryptographic memory isolation
- Patent number 10,776,525
- Issue date Sep 15, 2020
- Intel Corporation
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable on-die termination timing in a multi-rank system
- Patent number 10,680,613
- Issue date Jun 9, 2020
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent accesses of asymmetrical memory sources
- Patent number 10,558,570
- Issue date Feb 11, 2020
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable on-die termination timing in a multi-rank system
- Patent number 10,141,935
- Issue date Nov 27, 2018
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precharging and refreshing banks in memory device with bank group a...
- Patent number 10,109,340
- Issue date Oct 23, 2018
- Intel Corporation
- Kuljit S Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Polarity based data transfer function for volatile memory
- Patent number 10,055,346
- Issue date Aug 21, 2018
- Intel Corporation
- Nadav Bonen
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die termination control without a dedicated pin in a multi-rank...
- Patent number 9,948,299
- Issue date Apr 17, 2018
- Intel Corporation
- Kuljit S. Bains
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-die termination control without a dedicated pin in a multi-rank...
- Patent number 9,871,519
- Issue date Jan 16, 2018
- Intel Corporation
- Kuljit S. Bains
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Performing local power gating in a processor
- Patent number 9,772,674
- Issue date Sep 26, 2017
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polarity based data transfer function for volatile memory
- Patent number 9,740,610
- Issue date Aug 22, 2017
- Intel Corporation
- Nadav Bonen
- G11 - INFORMATION STORAGE
Information Patent Grant
Precharging and refreshing banks in memory device with bank group a...
- Patent number 9,728,245
- Issue date Aug 8, 2017
- Intel Corporation
- Kuljit S Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Avoiding DQS false sampling triggers
- Patent number 9,640,277
- Issue date May 2, 2017
- Intel Corporation
- Nadav Bonen
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetric set combined cache
- Patent number 9,582,430
- Issue date Feb 28, 2017
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing local power gating in a processor
- Patent number 9,229,524
- Issue date Jan 5, 2016
- Intel Corporation
- Nadav Bonen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic priority control based on latency tolerance
- Patent number 8,959,266
- Issue date Feb 17, 2015
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC ALLOCATION SCHEMES IN MEMORY SIDE CACHE FOR BANDWIDTH AND P...
- Publication number 20240220408
- Publication date Jul 4, 2024
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATING A MEMORY SIDE CACHE DATA ARRAY AND CACHE CONTROLLER
- Publication number 20240211400
- Publication date Jun 27, 2024
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...
- Publication number 20240202124
- Publication date Jun 20, 2024
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY POWER MANAGEMENT METHOD AND APPARATUS
- Publication number 20220262427
- Publication date Aug 18, 2022
- Intel Corporation
- Nivedha Krishnakumar
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MANAGEMENT TO IMPROVE POWER PERFORMANCE
- Publication number 20210405892
- Publication date Dec 30, 2021
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
- Publication number 20210103682
- Publication date Apr 8, 2021
- Intel Corporation
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
- Publication number 20190102577
- Publication date Apr 4, 2019
- Intel Corporation
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION
- Publication number 20190042157
- Publication date Feb 7, 2019
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM
- Publication number 20190036531
- Publication date Jan 31, 2019
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20180129265
- Publication date May 10, 2018
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20180129266
- Publication date May 10, 2018
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY
- Publication number 20180067852
- Publication date Mar 8, 2018
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...
- Publication number 20180025773
- Publication date Jan 25, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20170371397
- Publication date Dec 28, 2017
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL MEMORY MANAGEMENT
- Publication number 20170300415
- Publication date Oct 19, 2017
- Intel Corporation
- Nadav BONEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK...
- Publication number 20170194962
- Publication date Jul 6, 2017
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM
- Publication number 20170093400
- Publication date Mar 30, 2017
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK...
- Publication number 20170077928
- Publication date Mar 16, 2017
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC SET COMBINED CACHE
- Publication number 20160283392
- Publication date Sep 29, 2016
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...
- Publication number 20160254044
- Publication date Sep 1, 2016
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY
- Publication number 20160188463
- Publication date Jun 30, 2016
- Intel Corporation
- NADAV BONEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20160085287
- Publication date Mar 24, 2016
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING DQS FALSE SAMPLING TRIGGERS
- Publication number 20150186328
- Publication date Jul 2, 2015
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE
- Publication number 20150039790
- Publication date Feb 5, 2015
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20140006817
- Publication date Jan 2, 2014
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for driving and routing source operands to exe...
- Publication number 20040128572
- Publication date Jul 1, 2004
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING

Nadav Bonen

Person

Patents Grantslast 30 patents

Memory power management method and apparatus

Multi-tenant cryptographic memory isolation

Memory management to improve power performance

Architecture for dynamic transformation of memory configuration

Performing local power gating in a processor

Multi-tenant cryptographic memory isolation

Programmable on-die termination timing in a multi-rank system

Concurrent accesses of asymmetrical memory sources

Programmable on-die termination timing in a multi-rank system

Precharging and refreshing banks in memory device with bank group a...

Polarity based data transfer function for volatile memory

On-die termination control without a dedicated pin in a multi-rank...

On-die termination control without a dedicated pin in a multi-rank...

Performing local power gating in a processor

Polarity based data transfer function for volatile memory

Precharging and refreshing banks in memory device with bank group a...

Avoiding DQS false sampling triggers

Asymmetric set combined cache

Performing local power gating in a processor

Dynamic priority control based on latency tolerance

Patents Applicationslast 30 patents

DYNAMIC ALLOCATION SCHEMES IN MEMORY SIDE CACHE FOR BANDWIDTH AND P...

DISAGGREGATING A MEMORY SIDE CACHE DATA ARRAY AND CACHE CONTROLLER

SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...

MEMORY POWER MANAGEMENT METHOD AND APPARATUS

MEMORY MANAGEMENT TO IMPROVE POWER PERFORMANCE

MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION

MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION

ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION

PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM

Performing Local Power Gating In A Processor

Performing Local Power Gating In A Processor

POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY

PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...

Performing Local Power Gating In A Processor

ASYMMETRICAL MEMORY MANAGEMENT

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK...

PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK...

ASYMMETRIC SET COMBINED CACHE

PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...

POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY

Performing Local Power Gating In A Processor

AVOIDING DQS FALSE SAMPLING TRIGGERS

DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE

Performing Local Power Gating In A Processor

Apparatus and method for driving and routing source operands to exe...