Nader Amini

Person

Boca Raton, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Computer system and method for snooping date writes to cacheable me...
- Patent number 5,966,728
- Issue date Oct 12, 1999
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with varied data transfer speeds between system com...
- Patent number 5,761,533
- Issue date Jun 2, 1998
- International Business Machines Corporation
- Alfredo Aldereguia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snooping of I/O bus and invalidation of processor cache for memory...
- Patent number 5,673,414
- Issue date Sep 30, 1997
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining address location and taking on...
- Patent number 5,659,696
- Issue date Aug 19, 1997
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional data buffer for a bus-to-bus interface unit in a comp...
- Patent number 5,644,729
- Issue date Jul 1, 1997
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management of DMA slaves with DMA traps
- Patent number 5,619,729
- Issue date Apr 8, 1997
- Intel Corporation
- Patrick M. Bland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus read prefetch logic for improving information transfers...
- Patent number 5,581,714
- Issue date Dec 3, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus pacing logic for improving information transfers in a mu...
- Patent number 5,564,026
- Issue date Oct 8, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Expandable high performance FIFO design which includes memory cells...
- Patent number 5,551,009
- Issue date Aug 27, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic bus sizing of DMA transfers
- Patent number 5,548,786
- Issue date Aug 20, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a bus interface unit for overriding a normal arbitrat...
- Patent number 5,544,346
- Issue date Aug 6, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for counting the number of peripheral buses in each hierarch...
- Patent number 5,542,055
- Issue date Jul 30, 1996
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge for a multiple bus information handling system th...
- Patent number 5,522,050
- Issue date May 28, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge for a multiple bus information handling system th...
- Patent number 5,499,346
- Issue date Mar 12, 1996
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System direct memory access (DMA) support logic for PCI based compu...
- Patent number 5,450,551
- Issue date Sep 12, 1995
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing back-to-back data transfers in a...
- Patent number 5,448,703
- Issue date Sep 5, 1995
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitration logic for multiple bus computer system
- Patent number 5,396,602
- Issue date Mar 7, 1995
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA controller including a FIFO register and a residual register fo...
- Patent number 5,381,538
- Issue date Jan 10, 1995
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and recovery in a DMA controller
- Patent number 5,333,274
- Issue date Jul 26, 1994
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity error detection and recovery
- Patent number 5,313,627
- Issue date May 17, 1994
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling bus allocation using arbitration hold
- Patent number 5,301,282
- Issue date Apr 5, 1994
- International Business Machines Corp.
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitration control logic for computer system having dual bus archi...
- Patent number 5,265,211
- Issue date Nov 23, 1993
- International Business Machines Corporation
- Nader Amini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interface logic for computer system having dual bus architecture
- Patent number 5,255,374
- Issue date Oct 19, 1993
- International Business Machines Corporation
- Alfredo Aldereguia
- G06 - COMPUTING CALCULATING COUNTING

Nader Amini

Person

Patents Grantslast 30 patents

Computer system and method for snooping date writes to cacheable me...

Computer system with varied data transfer speeds between system com...

Snooping of I/O bus and invalidation of processor cache for memory...

Method and apparatus for determining address location and taking on...

Bidirectional data buffer for a bus-to-bus interface unit in a comp...

Power management of DMA slaves with DMA traps

Bus-to-bus read prefetch logic for improving information transfers...

Bus-to-bus pacing logic for improving information transfers in a mu...

Expandable high performance FIFO design which includes memory cells...

Dynamic bus sizing of DMA transfers

System having a bus interface unit for overriding a normal arbitrat...

System for counting the number of peripheral buses in each hierarch...

Bus-to-bus bridge for a multiple bus information handling system th...

Bus-to-bus bridge for a multiple bus information handling system th...

System direct memory access (DMA) support logic for PCI based compu...

Method and apparatus for providing back-to-back data transfers in a...

Arbitration logic for multiple bus computer system

DMA controller including a FIFO register and a residual register fo...

Error detection and recovery in a DMA controller

Parity error detection and recovery

Controlling bus allocation using arbitration hold

Arbitration control logic for computer system having dual bus archi...

Bus interface logic for computer system having dual bus architecture