NADIA RAHHAL-ORABI

Person

LAKE OSWEGO, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned contacts
- Patent number 11,887,891
- Issue date Jan 30, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ingaas epi structure and wet etch process for enabling III-v GAA in...
- Patent number 11,631,737
- Issue date Apr 18, 2023
- Intel Corporation
- Sanaz K. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 11,600,524
- Issue date Mar 7, 2023
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimizing gate profile for performance and gate fill
- Patent number 11,205,707
- Issue date Dec 21, 2021
- Intel Corporation
- Nadia M. Rahhal-Orabi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,930,557
- Issue date Feb 23, 2021
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential work function between gate stack metals to reduce para...
- Patent number 10,797,150
- Issue date Oct 6, 2020
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,629,483
- Issue date Apr 21, 2020
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with a sub-fin dielectric region under a gate
- Patent number 10,580,865
- Issue date Mar 3, 2020
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Well-based integration of heteroepitaxial N-type transistors with P...
- Patent number 10,461,082
- Issue date Oct 29, 2019
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High electron mobility transistors with localized sub-fin isolation
- Patent number 10,431,690
- Issue date Oct 1, 2019
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,141,226
- Issue date Nov 27, 2018
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Internal spacers for nanowire transistors and method of fabrication...
- Patent number 9,935,205
- Issue date Apr 3, 2018
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Apparatus and methods of forming fin structures with asymmetric pro...
- Patent number 9,929,273
- Issue date Mar 27, 2018
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial material for stripping masking layers
- Patent number 9,916,988
- Issue date Mar 13, 2018
- Intel Corporation
- Shakuntala Sundararajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,892,967
- Issue date Feb 13, 2018
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Internal spacers for nanowire transistors and method of fabrication...
- Patent number 9,508,796
- Issue date Nov 29, 2016
- Intel Corporation
- Seiyon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,508,821
- Issue date Nov 29, 2016
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prevention of metal loss in wafer processing
- Patent number 9,305,771
- Issue date Apr 5, 2016
- Intel Corporation
- Shakuntala Sundararajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded memory device having MIM capacitor formed in excavated str...
- Patent number 9,224,794
- Issue date Dec 29, 2015
- Intel Corporation
- Steven Keating
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double patterning lithography techniques
- Patent number 9,142,421
- Issue date Sep 22, 2015
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,093,513
- Issue date Jul 28, 2015
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded memory device having MIM capacitor formed in excavated str...
- Patent number 8,441,057
- Issue date May 14, 2013
- Intel Corporation
- Steven J. Keating
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 8,436,404
- Issue date May 7, 2013
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for reducing contact to gate shorts
- Patent number 8,168,488
- Issue date May 1, 2012
- Intel Corporation
- Nadia Rahhal-Orabi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for reducing contact to gate shorts
- Patent number 7,968,395
- Issue date Jun 28, 2011
- Intel Corporation
- Nadia Rahhal-Orabi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of patterning a metal on a vertical sidewall of an excavated...
- Patent number 7,927,959
- Issue date Apr 19, 2011
- Intel Corporation
- Steven J. Keating
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming semiconductor contacts
- Patent number 7,709,866
- Issue date May 4, 2010
- Intel Corporation
- Nadia Rahhal-Orabi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for reducing contact to gate shorts
- Patent number 7,655,986
- Issue date Feb 2, 2010
- Intel Corporation
- Nadia Rahhal-Orabi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced nitride layers for metal oxide semiconductors
- Patent number 7,314,836
- Issue date Jan 1, 2008
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20240030067
- Publication date Jan 25, 2024
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20230154793
- Publication date May 18, 2023
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20210134673
- Publication date May 6, 2021
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20200251387
- Publication date Aug 6, 2020
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20190051558
- Publication date Feb 14, 2019
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH A SUB-FIN DIELECTRIC REGION UNDER A GATE
- Publication number 20180337235
- Publication date Nov 22, 2018
- Intel Corporation
- WILLY RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL WORK FUNCTION BETWEEN GATE STACK METALS TO REDUCE PARA...
- Publication number 20180315827
- Publication date Nov 1, 2018
- Intel Corporation
- Sean T. MA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH ELECTRON MOBILITY TRANSISTORS WITH LOCALIZED SUB-FIN ISOLATION
- Publication number 20180158957
- Publication date Jun 7, 2018
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P...
- Publication number 20180130801
- Publication date May 10, 2018
- Intel Corporation
- WILLY RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20180096891
- Publication date Apr 5, 2018
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH ASYMMETRIC PRO...
- Publication number 20180013000
- Publication date Jan 11, 2018
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTIMIZING GATE PROFILE FOR PERFORMANCE AND GATE FILL
- Publication number 20170330955
- Publication date Nov 16, 2017
- Intel Corporation
- NADIA M. RAHHAL-ORABI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH SIDEWALL LINER
- Publication number 20170323955
- Publication date Nov 9, 2017
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN CHANNEL REGION ON WIDE SUBFIN
- Publication number 20170323963
- Publication date Nov 9, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Uniform Layers Formed with Aspect Ratio Trench Based Processes
- Publication number 20170317187
- Publication date Nov 2, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN...
- Publication number 20170263706
- Publication date Sep 14, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION...
- Publication number 20170047452
- Publication date Feb 16, 2017
- Intel Corporation
- Seiyon KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20170040218
- Publication date Feb 9, 2017
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION...
- Publication number 20160211322
- Publication date Jul 21, 2016
- Intel Corporation
- Seiyon KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL MATERIAL FOR STRIPPING MASKING LAYERS
- Publication number 20160203999
- Publication date Jul 14, 2016
- SHAKUNTALA SUNDARARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned contacts
- Publication number 20160155815
- Publication date Jun 2, 2016
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREVENTION OF METAL LOSS IN WAFER PROCESSING
- Publication number 20150179463
- Publication date Jun 25, 2015
- Shakuntala Sundararajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES
- Publication number 20140017899
- Publication date Jan 16, 2014
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED...
- Publication number 20130234290
- Publication date Sep 12, 2013
- Steven Keating
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20130178033
- Publication date Jul 11, 2013
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned contacts
- Publication number 20110156107
- Publication date Jun 30, 2011
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS
- Publication number 20110136314
- Publication date Jun 9, 2011
- Nadia Rahhal-Orabi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED...
- Publication number 20110134583
- Publication date Jun 9, 2011
- Steve J. Keating
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Semiconductor Contacts
- Publication number 20100171156
- Publication date Jul 8, 2010
- Nadia Rahhal-Orabi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of patterning a metal on a vertical sidewall of an excavated...
- Publication number 20100079924
- Publication date Apr 1, 2010
- Steven J. Keating
- H01 - BASIC ELECTRIC ELEMENTS

NADIA RAHHAL-ORABI

Person

Patents Grantslast 30 patents

Self-aligned contacts

Ingaas epi structure and wet etch process for enabling III-v GAA in...

Self-aligned contacts

Optimizing gate profile for performance and gate fill

Self-aligned contacts

Differential work function between gate stack metals to reduce para...

Self-aligned contacts

Transistor with a sub-fin dielectric region under a gate

Well-based integration of heteroepitaxial N-type transistors with P...

High electron mobility transistors with localized sub-fin isolation

Self-aligned contacts

Internal spacers for nanowire transistors and method of fabrication...

Apparatus and methods of forming fin structures with asymmetric pro...

Sacrificial material for stripping masking layers

Self-aligned contacts

Internal spacers for nanowire transistors and method of fabrication...

Self-aligned contacts

Prevention of metal loss in wafer processing

Embedded memory device having MIM capacitor formed in excavated str...

Double patterning lithography techniques

Self-aligned contacts

Embedded memory device having MIM capacitor formed in excavated str...

Self-aligned contacts

Systems and methods for reducing contact to gate shorts

Systems and methods for reducing contact to gate shorts

Method of patterning a metal on a vertical sidewall of an excavated...

Method for forming semiconductor contacts

Systems and methods for reducing contact to gate shorts

Enhanced nitride layers for metal oxide semiconductors

Patents Applicationslast 30 patents

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

TRANSISTOR WITH A SUB-FIN DIELECTRIC REGION UNDER A GATE

DIFFERENTIAL WORK FUNCTION BETWEEN GATE STACK METALS TO REDUCE PARA...

HIGH ELECTRON MOBILITY TRANSISTORS WITH LOCALIZED SUB-FIN ISOLATION

WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P...

SELF-ALIGNED CONTACTS

APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH ASYMMETRIC PRO...

OPTIMIZING GATE PROFILE FOR PERFORMANCE AND GATE FILL

APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH SIDEWALL LINER

THIN CHANNEL REGION ON WIDE SUBFIN

Uniform Layers Formed with Aspect Ratio Trench Based Processes

INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN...

INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION...

SELF-ALIGNED CONTACTS

INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION...

SACRIFICIAL MATERIAL FOR STRIPPING MASKING LAYERS

Self-aligned contacts

PREVENTION OF METAL LOSS IN WAFER PROCESSING

DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES

METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED...

SELF-ALIGNED CONTACTS

Self-aligned contacts

SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS

METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED...

Method for Forming Semiconductor Contacts

Method of patterning a metal on a vertical sidewall of an excavated...