Nagaraj N. Savithri

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Determination of clock path delays and implementation of a circuit...
- Patent number 10,289,784
- Issue date May 14, 2019
- Xilinx, Inc.
- Chiao K. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing verification in a programmable circuit design using variatio...
- Patent number 10,162,916
- Issue date Dec 25, 2018
- Xilinx, Inc.
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area-efficient performance monitors for adaptive voltage scaling
- Patent number 9,915,696
- Issue date Mar 13, 2018
- Xilinx, Inc.
- Nagaraj Savithri
- G01 - MEASURING TESTING
Information Patent Grant
Speed model tuning for programmable integrated circuits with consid...
- Patent number 9,885,750
- Issue date Feb 6, 2018
- Xilinx, Inc.
- Nagaraj Savithri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generation of delay values for a simulation model of circuit elemen...
- Patent number 9,639,640
- Issue date May 2, 2017
- Xilinx, Inc.
- Nagaraj Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing critical paths of a circuit design
- Patent number 9,501,604
- Issue date Nov 22, 2016
- Xilinx, Inc.
- Geetesh More
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of path delays in circuit designs
- Patent number 9,405,871
- Issue date Aug 2, 2016
- Xilinx, Inc.
- Nagaraj Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect speed model characterization in programmable integrate...
- Patent number 9,372,948
- Issue date Jun 21, 2016
- Xilinx, Inc.
- Nagaraj Savithri
- G01 - MEASURING TESTING
Information Patent Grant
Generating delay values for different contexts of a circuit
- Patent number 9,065,446
- Issue date Jun 23, 2015
- Xilinx, Inc.
- Nagaraj Savithri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 8,112,737
- Issue date Feb 7, 2012
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multi-mode circuit and a method for preventing degradation in the m...
- Patent number 8,013,635
- Issue date Sep 6, 2011
- Texas Instruments Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for positioning sub-resolution assist features
- Patent number 7,694,269
- Issue date Apr 6, 2010
- Texas Instruments Incorporated
- Nagaraj Savithri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 7,441,218
- Issue date Oct 21, 2008
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for circuit sensitivity driven parasitic extraction
- Patent number 7,318,208
- Issue date Jan 8, 2008
- Texas Instruments Incorporated
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for capacitance measurement in silicon
- Patent number 7,129,696
- Issue date Oct 31, 2006
- Texas Instruments Incorporated
- Nagaraj Narasimh Savithri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for modeling inductive effects on circuit performance
- Patent number 7,109,738
- Issue date Sep 19, 2006
- Texas Instruments Incorporated
- Nagaraj Narasimh Savithri
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell-based noise characterization and evaluation
- Patent number 6,732,339
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density parasitic measurement structure
- Patent number 6,700,399
- Issue date Mar 2, 2004
- Texas Instruments Incorporated
- Nagaraj Narasimh Savithri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for verification of crosstalk noise in a CMOS design
- Patent number 6,499,131
- Issue date Dec 24, 2002
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell-based noise characterization and evaluation
- Patent number 6,493,853
- Issue date Dec 10, 2002
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of simulation for gate oxide integrity check on an entire IC
- Patent number 6,378,109
- Issue date Apr 23, 2002
- Texas Instruments Incorporated
- Duane J. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for hierarchical parasitic extraction of a CMOS design
- Patent number 6,363,516
- Issue date Mar 26, 2002
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for analyzing circuit delays caused by capacitive coupling i...
- Patent number 6,253,359
- Issue date Jun 26, 2001
- Texas Instruments Incorporated
- Francisco A. Cano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining signal line interconnect width...
- Patent number 6,038,383
- Issue date Mar 14, 2000
- Texas Instruments Incorporated
- Duane J. Young
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE M...
- Publication number 20110193588
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FABRICATION MANAGEMENT SYSTEM
- Publication number 20090250698
- Publication date Oct 8, 2009
- Nagaraj Savithri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES
- Publication number 20090013297
- Publication date Jan 8, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES
- Publication number 20080203518
- Publication date Aug 28, 2008
- Nagaraj Savithri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Contact resistance and capacitance for semiconductor devices
- Publication number 20070277137
- Publication date Nov 29, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for modeling inductive effects on circuit performance
- Publication number 20060109021
- Publication date May 25, 2006
- Nagaraj Narasimh Savithri
- G01 - MEASURING TESTING
Information Patent Application
Method for circuit sensitivity driven parasitic extraction
- Publication number 20060085776
- Publication date Apr 20, 2006
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell-based noise characterization and evaluation
- Publication number 20030079191
- Publication date Apr 24, 2003
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING

Nagaraj N. Savithri

Person

Patents Grantslast 30 patents

Determination of clock path delays and implementation of a circuit...

Timing verification in a programmable circuit design using variatio...

Area-efficient performance monitors for adaptive voltage scaling

Speed model tuning for programmable integrated circuits with consid...

Generation of delay values for a simulation model of circuit elemen...

Testing critical paths of a circuit design

Determination of path delays in circuit designs

Interconnect speed model characterization in programmable integrate...

Generating delay values for different contexts of a circuit

Contact resistance and capacitance for semiconductor devices

Multi-mode circuit and a method for preventing degradation in the m...

Method for positioning sub-resolution assist features

Contact resistance and capacitance for semiconductor devices

Method for circuit sensitivity driven parasitic extraction

Method for capacitance measurement in silicon

Method for modeling inductive effects on circuit performance

Cell-based noise characterization and evaluation

High density parasitic measurement structure

Method for verification of crosstalk noise in a CMOS design

Cell-based noise characterization and evaluation

Method of simulation for gate oxide integrity check on an entire IC

Method for hierarchical parasitic extraction of a CMOS design

Method for analyzing circuit delays caused by capacitive coupling i...

Method and apparatus for determining signal line interconnect width...

Patents Applicationslast 30 patents

MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE M...

FABRICATION MANAGEMENT SYSTEM

CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES

METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES

Contact resistance and capacitance for semiconductor devices

Method for modeling inductive effects on circuit performance

Method for circuit sensitivity driven parasitic extraction

Cell-based noise characterization and evaluation