Nagarajan Ranganathan

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
MEMS devices and methods of forming thereof
- Patent number 11,767,217
- Issue date Sep 26, 2023
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Ranganathan Nagarajan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Piezoelectric MEMS devices and methods of forming thereof
- Patent number 11,631,800
- Issue date Apr 18, 2023
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jia Jie Xia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Piezoelectric microphone with deflection control and method of maki...
- Patent number 10,886,455
- Issue date Jan 5, 2021
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Jia Jie Xia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated circuits having shielded MEMS devices and methods for fa...
- Patent number 10,358,340
- Issue date Jul 23, 2019
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Humberto Campanella-Pineda
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated MEMS pressure sensor and MEMS inertial sensor
- Patent number 9,550,668
- Issue date Jan 24, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jia Jie Xia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Integrated MEMS-CMOS devices and methods for fabricating MEMS devic...
- Patent number 9,546,090
- Issue date Jan 17, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jia Jie Xia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Layer arrangement and a wafer level package comprising the layer ar...
- Patent number 9,240,362
- Issue date Jan 19, 2016
- Agency for Science, Technology and Research
- Vivek Chidambaram
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer level package and a method of forming a wafer level package
- Patent number 8,729,695
- Issue date May 20, 2014
- Agency for Science, Technology and Research
- Chirayarikathu Veedu Sankarapillai Premachandran
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of processing a wafer
- Patent number 8,603,917
- Issue date Dec 10, 2013
- Agency for Science, Technology and Research
- Woon Seong Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully salicided (FUCA) MOSFET structure
- Patent number 7,682,914
- Issue date Mar 23, 2010
- Agency for Science, Technololgy, and Research
- Patrick Guo Qiang Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RF and MMIC stackable micro-modules
- Patent number 7,592,703
- Issue date Sep 22, 2009
- Agency for Science, Technology and Research
- Vaidyanathan Kripesh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming through-wafer interconnects for vertical wafer le...
- Patent number 7,381,629
- Issue date Jun 3, 2008
- Agency for Science, Technology and Research
- Chirayarikathuveedu Premachandran Sankarapillai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of stacking thin substrates by transfer bonding
- Patent number 7,326,629
- Issue date Feb 5, 2008
- Agency for Science, Technology and Research
- Ranganathan Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully salicided (FUSA) MOSFET structure
- Patent number 7,294,890
- Issue date Nov 13, 2007
- Agency for Science, Technology and Research
- Patrick Guo Qiang Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RF and MMIC stackable micro-modules
- Patent number 7,230,318
- Issue date Jun 12, 2007
- Agency for Science, Technology and Research
- Vaidyanathan Kripesh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming through-wafer interconnects for vertical wafer le...
- Patent number 7,183,176
- Issue date Feb 27, 2007
- Agency for Science, Technology and Research
- Chirayarikathuveedu Premachandran Sankarapillai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating micro-mirror switching device
- Patent number 6,858,459
- Issue date Feb 22, 2005
- Institute of Microelectronics
- Janak Singh
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer-level package for micro-electro-mechanical systems
- Patent number 6,846,725
- Issue date Jan 25, 2005
- Institute of Microelectronics
- Ranganathan Nagarajan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer-level inter-connector formation method
- Patent number 6,787,456
- Issue date Sep 7, 2004
- Agency for Science, Technology and Research
- Vaidyanathan Kripesh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature resist trimming process
- Patent number 6,716,570
- Issue date Apr 6, 2004
- Institute of Microelectronics
- Ranganathan Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for fluid-based cooling of heat-generating dev...
- Patent number 6,717,812
- Issue date Apr 6, 2004
- Institute of Microelectronics
- Damaruganath Pinjala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Z-axis accelerometer
- Patent number 6,662,654
- Issue date Dec 16, 2003
- Institute of Microelectronics
- Yubo Miao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
High aspect ratio trench isolation process for surface micromachine...
- Patent number 6,573,154
- Issue date Jun 3, 2003
- Institute of Microelectronics
- Uppili Sridhar
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Z-axis accelerometer
- Patent number 6,571,628
- Issue date Jun 3, 2003
- Institute of Microelectronics
- Yubo Miao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Process for device using partial SOI
- Patent number 6,551,937
- Issue date Apr 22, 2003
- Institute of Microelectronics
- Cai Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral polysilicon beam process
- Patent number 6,461,888
- Issue date Oct 8, 2002
- Institute of Microelectronics
- Uppili Sridhar
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
MEMS DEVICES AND METHODS OF FORMING THEREOF
- Publication number 20220144625
- Publication date May 12, 2022
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Ranganathan NAGARAJAN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS DEVICES AND METHODS OF FORMING THEREOF
- Publication number 20210130162
- Publication date May 6, 2021
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Ranganathan NAGARAJAN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF MAKING PIEZOELECTRIC MICROPHONE WITH DEFLECTION CONTROL
- Publication number 20210083169
- Publication date Mar 18, 2021
- VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
- Jia Jie Xia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PIEZOELECTRIC MEMS DEVICES AND METHODS OF FORMING THEREOF
- Publication number 20210050506
- Publication date Feb 18, 2021
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jia Jie XIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PIEZOELECTRIC MICROPHONE WITH DEFLECTION CONTROL AND METHOD OF MAKI...
- Publication number 20190036003
- Publication date Jan 31, 2019
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jia Jie XIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS HAVING SHIELDED MEMS DEVICES AND METHODS FOR FA...
- Publication number 20170313577
- Publication date Nov 2, 2017
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Humberto Campanella Pineda
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATED MEMS-CMOS DEVICES AND INTEGRATED CIRCUITS WITH MEMS DEVI...
- Publication number 20170121172
- Publication date May 4, 2017
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jia Jie Xia
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER AR...
- Publication number 20150130039
- Publication date May 14, 2015
- Agency for Science, Technology and Research
- Vivek Chidambaram
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS
- Publication number 20150048509
- Publication date Feb 19, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Ranganathan NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Package and a Method of Forming a Wafer Level Package
- Publication number 20130020713
- Publication date Jan 24, 2013
- Chirayarikathu Veedu Sankarapillai Premachandran
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF PROCESSING A WAFER
- Publication number 20120178258
- Publication date Jul 12, 2012
- Agency For Science, Technology and Research
- Woon Seong Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC PACKAGE AND METHOD OF ASSEMBLING THE SAME
- Publication number 20100187682
- Publication date Jul 29, 2010
- Damaruganath Pinjala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROFLUIDIC DEVICE FOR ANALYZING THE STATUS OF A PARTICLE
- Publication number 20100015008
- Publication date Jan 21, 2010
- Agency for Science, Technology and Research
- Wee Liat Ong
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Fully salicided (FUCA) MOSFET structure
- Publication number 20080064153
- Publication date Mar 13, 2008
- Agency For Science, Technology and Research
- Patrick Guo Qiang Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RF and MMIC stackable micro-modules
- Publication number 20070222083
- Publication date Sep 27, 2007
- Agency For Science, Technology and Research
- Vaidyanathan Kripesh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of forming through-wafer interconnects for vertical wafer le...
- Publication number 20070141804
- Publication date Jun 21, 2007
- Chirayarikathuveedu Premachandran Sankarapillai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully salicided (FUSA) MOSFET structure
- Publication number 20060199321
- Publication date Sep 7, 2006
- Agency For Science, Technology and Research
- Patrick Guo Qiang Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of stacking thin substrates by transfer bonding
- Publication number 20060057836
- Publication date Mar 16, 2006
- Agency For Science, Technology and Research
- Ranganathan Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming through-wafer interconnects for vertical wafer le...
- Publication number 20060046432
- Publication date Mar 2, 2006
- Agency For Science, Technology and Research
- Chirayarikathuveedu Premachandran Sankarapillai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RF and MMIC stackable micro-modules
- Publication number 20050146049
- Publication date Jul 7, 2005
- Agency For Science, Technology and Research
- Vaidyanathan Kripesh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
WAFER-LEVEL INTER-CONNECTOR FORMATION METHOD
- Publication number 20040185593
- Publication date Sep 23, 2004
- Vaidyanathan Kripesh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sloped trench etching process
- Publication number 20040178171
- Publication date Sep 16, 2004
- Ranganathan Nagarajan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Wafer-level package for micro-electro-mechanical systems
- Publication number 20040077154
- Publication date Apr 22, 2004
- Ranganathan Nagarajan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Low temperature resist trimming process
- Publication number 20030219683
- Publication date Nov 27, 2003
- Institute of Microelectronics
- Ranganathan Nagarajan
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD OF FABRICATING MICRO-MIRROR SWITCHING DEVICE
- Publication number 20030218227
- Publication date Nov 27, 2003
- Institute of Microelectronics
- Janak Singh
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Z-AXIS ACCELEROMETER
- Publication number 20030209076
- Publication date Nov 13, 2003
- Institute of Microelectronics
- Yubo Miao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Process for device using partial SOI
- Publication number 20030040185
- Publication date Feb 27, 2003
- Institute of Microelectronics
- Cai Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sloped trench etching process
- Publication number 20020166838
- Publication date Nov 14, 2002
- Institute of Microelectronics
- Ranganathan Nagarajan
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Nagarajan Ranganathan

Person

Patents Grantslast 30 patents

MEMS devices and methods of forming thereof

Piezoelectric MEMS devices and methods of forming thereof

Piezoelectric microphone with deflection control and method of maki...

Integrated circuits having shielded MEMS devices and methods for fa...

Integrated MEMS pressure sensor and MEMS inertial sensor

Integrated MEMS-CMOS devices and methods for fabricating MEMS devic...

Layer arrangement and a wafer level package comprising the layer ar...

Wafer level package and a method of forming a wafer level package

Method of processing a wafer

Fully salicided (FUCA) MOSFET structure

RF and MMIC stackable micro-modules

Method of forming through-wafer interconnects for vertical wafer le...

Method of stacking thin substrates by transfer bonding

Fully salicided (FUSA) MOSFET structure

RF and MMIC stackable micro-modules

Method of forming through-wafer interconnects for vertical wafer le...

Method of fabricating micro-mirror switching device

Wafer-level package for micro-electro-mechanical systems

Wafer-level inter-connector formation method

Low temperature resist trimming process

Apparatus and method for fluid-based cooling of heat-generating dev...

Z-axis accelerometer

High aspect ratio trench isolation process for surface micromachine...

Z-axis accelerometer

Process for device using partial SOI

Lateral polysilicon beam process

Patents Applicationslast 30 patents

MEMS DEVICES AND METHODS OF FORMING THEREOF

MEMS DEVICES AND METHODS OF FORMING THEREOF

METHOD OF MAKING PIEZOELECTRIC MICROPHONE WITH DEFLECTION CONTROL

PIEZOELECTRIC MEMS DEVICES AND METHODS OF FORMING THEREOF

PIEZOELECTRIC MICROPHONE WITH DEFLECTION CONTROL AND METHOD OF MAKI...

INTEGRATED CIRCUITS HAVING SHIELDED MEMS DEVICES AND METHODS FOR FA...

INTEGRATED MEMS-CMOS DEVICES AND INTEGRATED CIRCUITS WITH MEMS DEVI...

LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER AR...

CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS

Wafer Level Package and a Method of Forming a Wafer Level Package

METHOD OF PROCESSING A WAFER

ELECTRONIC PACKAGE AND METHOD OF ASSEMBLING THE SAME

MICROFLUIDIC DEVICE FOR ANALYZING THE STATUS OF A PARTICLE

Fully salicided (FUCA) MOSFET structure

RF and MMIC stackable micro-modules

Method of forming through-wafer interconnects for vertical wafer le...

Fully salicided (FUSA) MOSFET structure

Method of stacking thin substrates by transfer bonding

Method of forming through-wafer interconnects for vertical wafer le...

RF and MMIC stackable micro-modules

WAFER-LEVEL INTER-CONNECTOR FORMATION METHOD

Sloped trench etching process

Wafer-level package for micro-electro-mechanical systems

Low temperature resist trimming process

METHOD OF FABRICATING MICRO-MIRROR SWITCHING DEVICE

Z-AXIS ACCELEROMETER

Process for device using partial SOI

Sloped trench etching process